Enhance Pipeline Controller and Register with AXI-Like Handshaking and Register Rebalancing
- Introduce comprehensive documentation for Pipeline Controller and Register, detailing core functions, generics, ports, and processes. Focus on data flow control, validity control, adjustability, and register rebalancing mechanisms. - Implement AXI-Like handshaking in Pipeline Controller for improved input and output data handling, supporting active-high ready and valid signals for efficient data transfer. - Refine Pipeline Register with register rebalancing options (no, yes, forward, backward) to optimize combinatorial logic pipelining in synthesis, configurable via `G_RegisterBalancing` generic. - Update generics and ports descriptions to reflect the inclusion of I/O FFs in pipeline depth calculation and clarify the reset active level and handshaking protocol. - Extend VHDL source for both modules to embody described functionalities and adjustments, ensuring alignment with documentation enhancements. - Augment testbench `Pipeline_tb.vhd` with random intervals for write and read operations, emphasizing dynamic testing scenarios.
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## Diagram
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## Description
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- Name: **Pipeline Controller**
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- Version: 0.0.1
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- Author: _Maximilian Passarello ([Blog](mpassarello.de))_
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- License: [MIT](LICENSE)
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The Pipeline Controller provides an easy way to construct a pipeline
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with AXI-Like handshaking at the input and output of the pipeline.
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### Core functions
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- **Data flow control**: Data flow control is implemented via handshaking at the input and output ports.
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- **Validity control**: The controller keeps the validity of the data in the individual pipeline stages under control.
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- **Adjustability**: The pipeline controller can be customized via the generics.
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### Generics
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Use the generic `G_PipelineStages` to set how deep the pipeline is.
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This depth contains all the registers associated with the pipeline.
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For example, for an _I_FF ⇨ Combinatorics ⇨ O_FF_ construction, the generic must be set to **2**.
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The active level of the reset input can also be set.
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### Clock Enable
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The `I_CE` port is active high and, when deactivated,
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effectively switches on the acceptance or output of data via handshaking in addition to the pipeline.
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### Reset
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A reset is explicitly **not** necessary on the pipeline registers.
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The validity of the data is kept under control via the pipeline controller
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and only this requires a dedicated reset if necessary.
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### Pipeline control
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You must connect the `O_Enable` port to the CE input of the corresponding pipeline registers.
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This is used to activate or deactivate the pipeline in full or via CE deactivated state.
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### AXI like Handshaking
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- **Input**: The `O_Ready` (active high) port is used to signal to the data-supplying component that data should be accepted.
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If it switches on `I_Valid` (active high), this in turn signals that data is ready to be accepted at its output.
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If both ports are active at the same time, the transfer is executed.
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- **Output**: The process runs analogously at the pipeline output.
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## History
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- 0.0.1 (2024-03-24) Initial version
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## Generics
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| Generic name | Type | Value | Description |
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| ---------------- | --------- | ----- | ------------------------- |
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| G_PipelineStages | integer | 3 | Number of pipeline stages |
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| G_ResetActiveAt | std_logic | '1' | Reset active at: |
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| Generic name | Type | Value | Description |
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| ---------------- | --------- | ----- | ----------------------------------------------------------------- |
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| G_PipelineStages | integer | 3 | Number of pipeline stages (FFs in the pipeline including I/O FFs) |
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| G_ResetActiveAt | std_logic | '1' | Reset active at this level |
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## Ports
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| Port name | Direction | Type | Description |
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| -------------------- | --------- | ----------- | -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- |
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| I_CLK | in | std_logic | Clock signal; **Rising edge** triggered |
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| I_RST | in | std_logic | Reset signal; Active at `G_ResetActiveAt` |
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| I_CE | in | std_logic | Chip enable; Active high |
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| O_Enable | out | std_logic | Pipeline enable; Active high when pipeline can accept data and `I_CE` is high. <br> **Note:** Connect to `I_Enable` of the registers to be controlled by this controller. |
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| Input-AXI-Handshake | in | Virtual bus | Input AXI like Handshake |
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| Output-AXI-Handshake | out | Virtual bus | Output AXI like Handshake |
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| Port name | Direction | Type | Description |
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| -------------------- | --------- | ----------- | ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- |
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| I_CLK | in | std_logic | Clock signal; **Rising edge** triggered |
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| I_RST | in | std_logic | Reset signal; Active at `G_ResetActiveAt` |
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| I_CE | in | std_logic | Chip enable; Active high |
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| O_Enable | out | std_logic | Pipeline enable; Active high when pipeline can accept data and `I_CE` is high. <br> **Note:** Connect `CE` of the registers to be controlled by this controller to `O_Enable`. |
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| Input-AXI-Handshake | in | Virtual bus | Input AXI like Handshake |
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| Output-AXI-Handshake | out | Virtual bus | Output AXI like Handshake |
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### Virtual Buses
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| C_Ready | std_logic | Ready signal for the pipeline controller to indicate that the pipeline can accept data; <br> mapped to `O_Enable` and `O_Ready` ports. |
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## Processes
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- P_Flags: ( R_Valid, I_Ready )
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- P_ExternalFlags: ( R_Valid, C_Ready, I_CE )
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- **Description**
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Produce the `C_Ready` signal for the pipeline controller, controlling the data flow in the pipeline.
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Produce the `O_Valid`, `O_Enable`, and `O_Ready` signals for the pipeline controller. <br> - `O_Enable`, and `O_Ready` are **and** combined from the `C_Ready` and `I_CE` signals. <br> - `O_Valid` is the last bit of the `R_Valid` signal and represents the validity of the data in the last stage of the pipeline.
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- P_InternalFlags: ( R_Valid, I_Ready )
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- **Description**
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Produce the `C_Ready` signal for the pipeline controller, controlling the data flow in the pipeline. <br> `C_Ready` is asserted when the data is available in the last stage of the pipeline **and** the external component is ready to accept data **or** when no data is available in the last stage of the pipeline.
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- P_ValidPipeline: ( I_CLK )
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- **Description**
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Shift the pipeline stages with `R_Valid` signal as placeholder to control the pipeline stages.
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Shift the pipeline stages with `R_Valid` signal as placeholder to control the validity of the data in the individual pipeline stages.
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