HDL/Pipeline-AXI-Handshake
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Optimizes pipeline and clock configuration

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Refactors pipeline architecture by separating input and output stages.
Introduces additional controllers and registers for better modularity.
Aligns signal and attribute formatting for improved readability.
This commit is contained in:
0xMax42
2025-04-16 17:27:18 +00:00
parent d320c31aea
commit 6c6c285e79
2 changed files with 71 additions and 34 deletions
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3
src/Pipeline_pb.ucf
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@@ -1,3 +1,4 @@
#NET I_CLK LOC = AG18;
NET I_CLK LOC = B8; NET I_CLK LOC = B8;
NET I_CLK TNM_NET = CLOCK; NET I_CLK TNM_NET = CLOCK;
TIMESPEC TS_CLOCK = PERIOD CLOCK 240 MHz HIGH 50 %; TIMESPEC TS_CLOCK = PERIOD CLOCK 250 MHz HIGH 50 %;

52
src/Pipeline_pb.vhd
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@@ -12,7 +12,7 @@ use ieee.math_real.all;
entity Pipeline_pb is entity Pipeline_pb is
generic ( generic (
--@ Number of pipeline stages --@ Number of pipeline stages
G_PipelineStages : integer := 3; G_PipelineStages : integer := 10;
--@ Data width --@ Data width
G_Width : integer := 32; G_Width : integer := 32;
--@ Register balancing attribute<br> --@ Register balancing attribute<br>
@@ -64,7 +64,12 @@ architecture RTL of Pipeline_pb is
attribute keep of R_DataOut, R_ValidOut, R_ReadyIn : signal is "true"; attribute keep of R_DataOut, R_ValidOut, R_ReadyIn : signal is "true";
attribute IOB of R_DataOut, R_ValidOut, R_ReadyIn : signal is "false"; attribute IOB of R_DataOut, R_ValidOut, R_ReadyIn : signal is "false";
signal C_PipelineEnable : std_logic; signal C_Pipeline0Enable : std_logic;
signal C_Pipeline1Enable : std_logic;
signal R_Valid : std_logic;
signal R_Ready : std_logic;
signal R_Data : std_logic_vector(G_Width - 1 downto 0);
begin begin
BenchmarkEnvironmentFFs : process (I_CLK) BenchmarkEnvironmentFFs : process (I_CLK)
@@ -86,7 +91,7 @@ begin
end if; end if;
end process; end process;
PipelineController : entity work.PipelineController PipelineControllerIn : entity work.PipelineController
generic map( generic map(
G_PipelineStages => G_PipelineStages, G_PipelineStages => G_PipelineStages,
G_ResetActiveAt => '1' G_ResetActiveAt => '1'
@@ -95,14 +100,14 @@ begin
I_CLK => I_CLK, I_CLK => I_CLK,
I_RST => R_RST, I_RST => R_RST,
I_CE => R_CE, I_CE => R_CE,
O_Enable => C_PipelineEnable, O_Enable => C_Pipeline0Enable,
I_Valid => R_ValidIn, I_Valid => R_ValidIn,
O_Ready => R_ReadyOut, O_Ready => R_ReadyOut,
O_Valid => R_ValidOut, O_Valid => R_Valid,
I_Ready => R_ReadyIn I_Ready => R_Ready
); );
PipelineRegister : entity work.PipelineRegister PipelineRegisterIn : entity work.PipelineRegister
generic map( generic map(
G_PipelineStages => G_PipelineStages, G_PipelineStages => G_PipelineStages,
G_Width => G_Width, G_Width => G_Width,
@@ -110,8 +115,39 @@ begin
) )
port map( port map(
I_CLK => I_CLK, I_CLK => I_CLK,
I_Enable => C_PipelineEnable, I_Enable => C_Pipeline0Enable,
I_Data => R_DataIn, I_Data => R_DataIn,
O_Data => R_Data
);
---------
PipelineControllerOut : entity work.PipelineController
generic map(
G_PipelineStages => G_PipelineStages,
G_ResetActiveAt => '1'
)
port map(
I_CLK => I_CLK,
I_RST => R_RST,
I_CE => R_CE,
O_Enable => C_Pipeline1Enable,
I_Valid => R_Valid,
O_Ready => R_Ready,
O_Valid => R_ValidOut,
I_Ready => R_ReadyIn
);
PipelineRegisterOut : entity work.PipelineRegister
generic map(
G_PipelineStages => G_PipelineStages,
G_Width => G_Width,
G_RegisterBalancing => G_RegisterBalancing
)
port map(
I_CLK => I_CLK,
I_Enable => C_Pipeline1Enable,
I_Data => R_Data,
O_Data => R_DataOut O_Data => R_DataOut
); );