diff --git a/src/Pipeline_pb.ucf b/src/Pipeline_pb.ucf
index 21ce23c..9395e8c 100644
--- a/src/Pipeline_pb.ucf
+++ b/src/Pipeline_pb.ucf
@@ -1,3 +1,4 @@
+#NET I_CLK LOC = AG18;
NET I_CLK LOC = B8;
NET I_CLK TNM_NET = CLOCK;
-TIMESPEC TS_CLOCK = PERIOD CLOCK 240 MHz HIGH 50 %;
\ No newline at end of file
+TIMESPEC TS_CLOCK = PERIOD CLOCK 250 MHz HIGH 50 %;
\ No newline at end of file
diff --git a/src/Pipeline_pb.vhd b/src/Pipeline_pb.vhd
index a507c04..8b38341 100644
--- a/src/Pipeline_pb.vhd
+++ b/src/Pipeline_pb.vhd
@@ -12,67 +12,72 @@ use ieee.math_real.all;
entity Pipeline_pb is
generic (
--@ Number of pipeline stages
- G_PipelineStages : integer := 3;
+ G_PipelineStages : integer := 10;
--@ Data width
- G_Width : integer := 32;
+ G_Width : integer := 32;
--@ Register balancing attribute
--@ - "no" : No register balancing
--@ - "yes": Register balancing in both directions
--@ - "forward": Moves a set of FFs at the inputs of a LUT to a single FF at its output.
--@ - "backward": Moves a single FF at the output of a LUT to a set of FFs at its inputs.
- G_RegisterBalancing : string := "yes"
+ G_RegisterBalancing : string := "yes"
);
port (
- I_CLK : in std_logic;
- I_RST : in std_logic;
- I_CE : in std_logic;
- I_Data : in std_logic_vector(G_Width - 1 downto 0);
- I_Valid : in std_logic;
+ I_CLK : in std_logic;
+ I_RST : in std_logic;
+ I_CE : in std_logic;
+ I_Data : in std_logic_vector(G_Width - 1 downto 0);
+ I_Valid : in std_logic;
O_Ready : out std_logic;
O_Data : out std_logic_vector(G_Width - 1 downto 0);
O_Valid : out std_logic;
- I_Ready : in std_logic
+ I_Ready : in std_logic
);
end entity Pipeline_pb;
architecture RTL of Pipeline_pb is
-- Keep attribute: Prevents the synthesis tool from removing the entity if is "true".
- attribute keep : string;
+ attribute keep : string;
-- IOB attribute: Attaches the FF to the IOB if is "true".
- attribute IOB : string;
+ attribute IOB : string;
-- General Interace
- signal R_RST : std_logic;
- signal R_CE : std_logic;
+ signal R_RST : std_logic;
+ signal R_CE : std_logic;
-- Attribute
- attribute keep of R_RST, R_CE : signal is "true";
- attribute IOB of R_RST, R_CE : signal is "false";
+ attribute keep of R_RST, R_CE : signal is "true";
+ attribute IOB of R_RST, R_CE : signal is "false";
-- Input Interface
- signal R_DataIn : std_logic_vector(G_Width - 1 downto 0);
- signal R_ValidIn : std_logic;
- signal R_ReadyOut : std_logic;
+ signal R_DataIn : std_logic_vector(G_Width - 1 downto 0);
+ signal R_ValidIn : std_logic;
+ signal R_ReadyOut : std_logic;
-- Attribute
- attribute keep of R_DataIn, R_ValidIn, R_ReadyOut : signal is "true";
- attribute IOB of R_DataIn, R_ValidIn, R_ReadyOut : signal is "false";
+ attribute keep of R_DataIn, R_ValidIn, R_ReadyOut : signal is "true";
+ attribute IOB of R_DataIn, R_ValidIn, R_ReadyOut : signal is "false";
-- Output Interface
- signal R_DataOut : std_logic_vector(G_Width - 1 downto 0);
- signal R_ValidOut : std_logic;
- signal R_ReadyIn : std_logic;
+ signal R_DataOut : std_logic_vector(G_Width - 1 downto 0);
+ signal R_ValidOut : std_logic;
+ signal R_ReadyIn : std_logic;
-- Attribute
attribute keep of R_DataOut, R_ValidOut, R_ReadyIn : signal is "true";
attribute IOB of R_DataOut, R_ValidOut, R_ReadyIn : signal is "false";
- signal C_PipelineEnable : std_logic;
+ signal C_Pipeline0Enable : std_logic;
+ signal C_Pipeline1Enable : std_logic;
+
+ signal R_Valid : std_logic;
+ signal R_Ready : std_logic;
+ signal R_Data : std_logic_vector(G_Width - 1 downto 0);
begin
BenchmarkEnvironmentFFs : process (I_CLK)
begin
if rising_edge(I_CLK) then
-- General Interace
- R_RST <= I_RST;
- R_CE <= I_CE;
+ R_RST <= I_RST;
+ R_CE <= I_CE;
-- Input Interface
R_DataIn <= I_Data;
@@ -86,7 +91,7 @@ begin
end if;
end process;
- PipelineController : entity work.PipelineController
+ PipelineControllerIn : entity work.PipelineController
generic map(
G_PipelineStages => G_PipelineStages,
G_ResetActiveAt => '1'
@@ -95,14 +100,14 @@ begin
I_CLK => I_CLK,
I_RST => R_RST,
I_CE => R_CE,
- O_Enable => C_PipelineEnable,
+ O_Enable => C_Pipeline0Enable,
I_Valid => R_ValidIn,
O_Ready => R_ReadyOut,
- O_Valid => R_ValidOut,
- I_Ready => R_ReadyIn
+ O_Valid => R_Valid,
+ I_Ready => R_Ready
);
- PipelineRegister : entity work.PipelineRegister
+ PipelineRegisterIn : entity work.PipelineRegister
generic map(
G_PipelineStages => G_PipelineStages,
G_Width => G_Width,
@@ -110,9 +115,40 @@ begin
)
port map(
I_CLK => I_CLK,
- I_Enable => C_PipelineEnable,
+ I_Enable => C_Pipeline0Enable,
I_Data => R_DataIn,
+ O_Data => R_Data
+ );
+
+ ---------
+
+ PipelineControllerOut : entity work.PipelineController
+ generic map(
+ G_PipelineStages => G_PipelineStages,
+ G_ResetActiveAt => '1'
+ )
+ port map(
+ I_CLK => I_CLK,
+ I_RST => R_RST,
+ I_CE => R_CE,
+ O_Enable => C_Pipeline1Enable,
+ I_Valid => R_Valid,
+ O_Ready => R_Ready,
+ O_Valid => R_ValidOut,
+ I_Ready => R_ReadyIn
+ );
+
+ PipelineRegisterOut : entity work.PipelineRegister
+ generic map(
+ G_PipelineStages => G_PipelineStages,
+ G_Width => G_Width,
+ G_RegisterBalancing => G_RegisterBalancing
+ )
+ port map(
+ I_CLK => I_CLK,
+ I_Enable => C_Pipeline1Enable,
+ I_Data => R_Data,
O_Data => R_DataOut
);
-end architecture RTL;
\ No newline at end of file
+end architecture RTL;