Optimizes pipeline and clock configuration

Refactors pipeline architecture by separating input and output stages.
Introduces additional controllers and registers for better modularity.
Aligns signal and attribute formatting for improved readability.

src/Pipeline_pb.ucf

@@ -1,3 +1,4 @@
+#NET I_CLK	                    LOC = AG18; 
 NET I_CLK	                    LOC = B8; 
 NET I_CLK	                    TNM_NET = CLOCK;
-TIMESPEC TS_CLOCK = PERIOD CLOCK 240 MHz HIGH 50 %;
+TIMESPEC TS_CLOCK = PERIOD CLOCK 250 MHz HIGH 50 %;