fix: Corrects ready signal and data buffering logic

- Corrects the ready signal to properly reflect buffer status.
- Modifies data buffering logic to ensure proper data handling.
- Updates the ready signal to high when buffer is not full.

src/PipelineBufferController.vhd

@@ -41,27 +41,31 @@ architecture RTL of PipelineBufferController is
     signal C_Enable : std_logic := '0';
 
     signal R_IsBuffered : std_logic := '0';
+    signal R_Ready      : std_logic := '1';
 begin
 
     --@ Set mux to buffered mode if data is available in the buffer.
     C_MUX    <= R_IsBuffered;
     --@ Enable the buffer register if not buffered and chip enable is high.
     C_Enable <= I_CE and not R_IsBuffered;
-    --@ Set the ready signal to high if not buffered.
-    O_Ready  <= not R_IsBuffered;
     --@ Set the valid signal to high if data is available in the buffer or if data is valid.
     O_Valid  <= R_IsBuffered or I_Valid;
 
+    O_Ready <= R_Ready;
+
     process (I_CLK)
     begin
         if rising_edge(I_CLK) then
             if I_RST = G_ResetActiveAt then
                 R_IsBuffered <= '0';
+                R_Ready      <= '1';
             elsif I_CE = '1' then
                 if R_IsBuffered = '0' and I_Valid = '1' then
                     R_IsBuffered <= '1';
+                    R_Ready      <= '0';
                 elsif I_Ready = '1' and (R_IsBuffered or I_Valid) = '1' then
                     R_IsBuffered <= '0';
+                    R_Ready      <= '1';
                 end if;
             end if;
         end if;