Enhanced the GenericCounter VHDL module by adding a comprehensive set of features, including synchronous reset, clock enable, configurable counting direction, over- and underflow flags, and lookahead value. Introduced detailed project documentation, including a descriptive README, waveform diagrams in both SVG and JSON format, and a UCF constraints file specifying clock settings.
68 lines
1.5 KiB
JSON
68 lines
1.5 KiB
JSON
{
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"signal": [
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[
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"General",
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{
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"name": "CLK",
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"wave": "P.....|........",
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"node": "0123456789abcde",
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"period": 1
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},
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{
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"name": "RST",
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"wave": "10....|.....10."
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},
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{
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"name": "CE",
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"wave": "0.1...|........"
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}
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],
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[
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"Set",
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{
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"name": "Set",
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"wave": "0.....|..10...."
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},
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{
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"name": "SetValue",
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"wave": "x.....|..8x....",
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"data": [
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"5"
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]
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}
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],
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[
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"Counter",
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{
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"name": "CountEnable",
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"wave": "0..1..|.......0"
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},
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{
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"name": "CounterValue",
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"wave": "4..777|77777777",
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"data": "0 1 2 3 15 0 5 6 7 8 1 1"
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},
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{
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"name": "LookAheadValue",
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"wave": "4..777|77777777",
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"data": "1 2 3 4 0 1 6 7 8 9 2 2"
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}
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],
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[
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"Flags",
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{
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"name": "OverUnderflow",
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"wave": "0.....|.10....."
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}
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]
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],
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"config": {
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"hscale": 1
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},
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"head": {
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"text": "<b>Generic Counter</b>"
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},
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"foot": {
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"text": "RST Value = 0"
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}
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} |