Max P
08f3183b6e
Implemented proper address forwarding for read requests to the FIFO interface, ensuring correct functionality during data read operations. Documented the usage procedures for data reads and writes and refined the history and timing diagrams in the associated documentation for clarity. This update includes reorganizing comments for better readability and updating signal controls to synchronize address handling with data output.
149 lines
10 KiB
Markdown
149 lines
10 KiB
Markdown
# Entity: DEPP
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- **File**: DEPP.vhd
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## Diagram
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## Description
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An EPP interface for Digilent FPGA boards
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This interface is designed to be used with the Digilent EPP interface
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and the Digilent Adept software.
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**Measured data rate ≈ 4.68 kByte/s**
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## Usage
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The module is designed to be used with a FIFO interface.
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Either the data & address (**write**) are transferred via the FIFO interface
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**or** the requested address is transferred first and then the corresponding data is expected.
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### Data Write:
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With a data write request, the module transfers the **data** and the **address**
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to the two corresponding FIFO interfaces.
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### Data Read:
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With a data read request, the module transfers the **requested address**
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to the FIFO interface. It then expects the corresponding data
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via the data input FIFO.
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## History:
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- 0.2.0 (2010.05.30) Initial version
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- 0.3.0 (2024.03.06) Refactored and commented
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- 0.3.1 (2024.03.09) Complet overhaul of the module
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- 0.3.2 (2024.03.13) The forwarding of the address to be read to the FIFO is now implemented correctly.
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A usage description has been added. Documentation improved.
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## Timing diagrams of the EPP bus
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### EPP Address Write
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### EPP Data Write
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### EPP Data Read
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## Ports
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| Port name | Direction | Type | Description |
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| ---------------- | --------- | ----------- | ------------------------------------------------- |
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| CLK | in | std_logic | Clock signal Rising edge triggered |
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| CE | in | std_logic | Chip enable `1` = enabled, `0` = disabled |
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| RST | in | std_logic | Reset signal `1` = reset, `0` = normal operation |
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| EPP-Interface | out | Virtual bus | EPP Interface |
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| FIFO-Data-Out | out | Virtual bus | Data & Address Output. FIFO compatible interface |
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| FIFO-Data-In | in | Virtual bus | Data input. FIFO compatible interface |
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| FIFO-Address-Out | out | Virtual bus | Request address output. FIFO compatible interface |
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### Virtual Buses
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#### EPP-Interface
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| Port name | Direction | Type | Description |
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| ------------------ | --------- | ---------------------------- | ---------------------------------------------------------------------------------------------------------------------------------------------------------- |
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| DEPP_AddressEnable | in | std_logic | Address strobe |
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| DEPP_DataEnable | in | std_logic | Data strobe |
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| DEPP_WriteEnable | in | std_logic | Transfer direction control<br> `1` = read (Host from DEPP); `0` = write (Host to DEPP) |
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| DEPP_Wait | out | std_logic | Handshake signal <br> `0` = ready for new cycle; `1` = closing current cycle and not ready for new cycle<br> Keep the signal low to delay the cycle length |
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| DEPP_Bus | inout | std_logic_vector(7 downto 0) | Data/Adress bus; Tri-state |
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#### FIFO-Data-Out
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| Port name | Direction | Type | Description |
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| ----------------------- | --------- | ---------------------------- | ----------------------------------------------------------------------- |
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| DataOutFifo_Data | out | std_logic_vector(7 downto 0) | Data output corosponding to the address |
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| DataOutFifo_Address | out | std_logic_vector(7 downto 0) | Address output |
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| DataOutFifo_WriteEnable | out | std_logic | Valid data & adress output if `1`. Is only 1 cycle valid |
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| DataOutFifo_FullFlag | in | std_logic | If `1` the module delays the bus and dont rise the `WriteEnable` signal |
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#### FIFO-Data-In
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| Port name | Direction | Type | Description |
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| --------------------- | --------- | ---------------------------- | ------------------------------------------------------- |
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| DataInFifo_Data | in | std_logic_vector(7 downto 0) | Data input |
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| DataInFifo_EmptyFlag | in | std_logic | If the fifo is not empty, the module will read the data |
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| DataInFifo_ReadEnable | out | std_logic | Is one cycle `1` to indicate that the data is read |
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#### FIFO-Address-Out
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| Port name | Direction | Type | Description |
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| -------------------------- | --------- | ---------------------------- | ------------------------------------------------------------------------- |
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| AddressOutFifo_Data | out | std_logic_vector(7 downto 0) | Address output for read requests |
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| AddressOutFifo_WriteEnable | out | std_logic | Valid address output if `1`. Is only 1 cycle valid |
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| AddressOutFifo_FullFlag | in | std_logic | If `1` the module delays the bus and dont rise the `RequestEnable` signal |
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## Signals
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| Name | Type | Description |
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| ------------------------------ | ---------------------------- | --------------------------------------------------------------------------------------- |
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| TempAddressRegister | std_logic_vector(7 downto 0) | Catch the address as long as the mode (read/write) has not yet been decided. |
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| EPP_AddressEnableShiftRegister | std_logic_vector(1 downto 0) | Shift register for the rising/falling edge detection of the `DEPP_AddressEnable` signal |
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| EPP_DataEnableShiftRegister | std_logic_vector(1 downto 0) | Shift register for the rising/falling edge detection of the `DEPP_DataEnable` signal |
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| Mode | ModeType | The current state of the main state machine |
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| InterWriteEnableOut | std_logic | The output signals for the output data fifo; also controls the address fifo. |
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| InterRequestEnable | std_logic | The output signals for the output address fifo |
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| InterAddressEnable | std_logic | Intermediary signal to start the address write cycle |
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| DataInFifo_DataAviable | std_logic | Negated `DataInFifo_EmptyFlag` signal |
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## Types
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| Name | Type | Description |
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| -------- | ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | ------------------------------------ |
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| ModeType | (Idle,<br><span style="padding-left:20px"> RequestActive,<br><span style="padding-left:20px"> SetData,<br><span style="padding-left:20px"> WriteActive,<br><span style="padding-left:20px"> WaitForFallingDataEnable,<br><span style="padding-left:20px"> WaitingForFallingAddressEnable,<br><span style="padding-left:20px"> AdressActive) | The states of the main state machine |
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## Processes
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- EPP_AddressEnableCatch: ( CLK )
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- **Description**
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Shifts the value from the `DEPP_AddressEnable` signal into the `EPP_AddressEnableShiftRegister` for the rising/falling edge detection.
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- EPP_DataEnableCatch: ( CLK )
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- **Description**
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Shifts the value from the `DEPP_DataEnable` signal into the `EPP_DataEnableShiftRegister`. for the rising/falling edge detection.
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- DataInFIFOMinimizeLatency: ( Mode, DataInFifo_DataAviable )
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- **Description**
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Redirection of the `DataInFifo_EmptyFlag` signal to the `DataInFifo_ReadEnable` signal if in the `RequestActive` mode: Minimize the latency of the data read.
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- EPP_WaitManagement: ( CLK )
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- EPP_AddressCatch: ( CLK )
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- **Description**
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Address write cycle: If the `DEPP_AddressEnable` signal rises, he `DEPP_WriteEnable` signal is low and the module is in idle state the `DEPP_Bus` is stored in the `TempAddressRegister`.
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- EPP_ReciveData: ( CLK )
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- **Description**
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Data write cycle: If the `DEPP_DataEnable` signal rises, the `DEPP_WriteEnable` signal is low and the module is in idle state the `DEPP_Bus` is stored in the `DataOut`, the `TempAddressRegister` is stored in the `AddressOut` and the `WriteEnableOut` signal is set to `1`.
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- EPP_ReciveRequest: ( CLK )
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- **Description**
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Data read cycle: If the `DEPP_DataEnable` signal rises, the `DEPP_WriteEnable` signal is high (read) and the module is in idle state the `TempAddressRegister` is stored in the `RequestAddress` and the `RequestEnable` signal is set to `1`.
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## State machines
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