Max P
4f5642709c
Included new Logic Analyzer Captures section in README and created a corresponding markdown file with waveform images for various EPP cycles. This provides visual aids for better understanding the timing and behavior of EPP transactions.
60 lines
2.8 KiB
Markdown
60 lines
2.8 KiB
Markdown
# VHDL Module for the Digilent Asynchronous Parallel Port Interface (DEPP)
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## Overview
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The `DEPP.vhd` module is designed as an Enhanced Parallel Port (EPP) interface for use with Digilent FPGA boards. It facilitates communication between a host computer and the FPGA via the Digilent Adept software, supporting operations such as address write, data write, and data read cycles.
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## Features
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- Designed for integration with Digilent FPGA boards.
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- Supports data transfers with Digilent Adept software.
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- Measured data rate of approximately 4.68 kByte/s.
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## Bus Cycles Visualized
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- EPP Address Write Cycle
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- EPP Data Write Cycle
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- EPP Data Read Cycle
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### Logic Analyzer Captures
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The captures can be found in the [Logic Analyzer Captures](docs/Logic%20Analyzer%20Captures/Logic%20Analyzer%20Captures.md) directory.
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## Port Definitions
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| Port Name | Direction | Type | Description |
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| ---------------- | --------- | ----------- | -------------------------------------------------- |
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| CLK | in | std_logic | Clock signal. Rising edge triggered. |
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| CE | in | std_logic | Chip enable. `1` = enabled, `0` = disabled. |
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| RST | in | std_logic | Reset signal. `1` = reset, `0` = normal operation. |
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| EPP-Interface | out | Virtual bus | EPP Interface for address and data operations. |
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| FIFO-Data-Out | out | Virtual bus | FIFO compatible data and address output interface. |
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| FIFO-Data-In | in | Virtual bus | FIFO compatible data input interface. |
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| FIFO-Address-Out | out | Virtual bus | FIFO compatible request address output interface. |
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Detailed information on virtual bus port configurations can be found within the [module's documentation](docs/DEPP/DEPP.md).
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## Dependencies
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The module depends on standard logic and numeric libraries available in VHDL. Ensure you have the latest version of the Digilent Adept software for proper interfacing with the module.
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## Contributing
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Contributions to improve the module or extend its capabilities are welcome. Please adhere to the existing coding standards and provide documentation for any changes made.
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## License
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This module is open source and is distributed under the MIT license. Please see the [LICENSE](LICENSE) file for full details.
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## Acknowledgments
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Special thanks to the Digilent team for providing a reference manual in which the diagrams and the description in the text are contradictory ;-)
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