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Optimize FIFO interface logic

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0xMax42
2024-03-12 21:13:27 +01:00
parent aeea87325a
commit 70b28405a5
1 changed files with 2 additions and 2 deletions
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code/DEPP.vhd
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@@ -14,7 +14,7 @@
--@ **or** the requested address is transferred first and then the corresponding data is expected. --@ **or** the requested address is transferred first and then the corresponding data is expected.
--@ ### Data Write: --@ ### Data Write:
--@ With a data write request, the module transfers the **data** and the **address** --@ With a data write request, the module transfers the **data** and the **address**
--@ to the two corresponding FIFO interfaces. --@ to the corresponding FIFO interface.
--@ ### Data Read: --@ ### Data Read:
--@ With a data read request, the module transfers the **requested address** --@ With a data read request, the module transfers the **requested address**
--@ to the FIFO interface. It then expects the corresponding data --@ to the FIFO interface. It then expects the corresponding data
@@ -183,7 +183,7 @@ begin
DataInFifo_DataAviable <= not DataInFifo_EmptyFlag; DataInFifo_DataAviable <= not DataInFifo_EmptyFlag;
DataOutFifo_WriteEnable <= InterWriteEnableOut; DataOutFifo_WriteEnable <= InterWriteEnableOut;
AddressOutFifo_WriteEnable <= InterRequestEnable or InterWriteEnableOut; AddressOutFifo_WriteEnable <= InterRequestEnable;
--@ Shifts the value from the `DEPP_AddressEnable` signal into the `EPP_AddressEnableShiftRegister` --@ Shifts the value from the `DEPP_AddressEnable` signal into the `EPP_AddressEnableShiftRegister`
--@ for the rising/falling edge detection. --@ for the rising/falling edge detection.