From 70b28405a5b3b62c46798d2adb27c29258562ab2 Mon Sep 17 00:00:00 2001 From: Max P Date: Tue, 12 Mar 2024 21:13:27 +0100 Subject: [PATCH] Optimize FIFO interface logic --- code/DEPP.vhd | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/code/DEPP.vhd b/code/DEPP.vhd index e53eeab..f878e38 100644 --- a/code/DEPP.vhd +++ b/code/DEPP.vhd @@ -14,7 +14,7 @@ --@ **or** the requested address is transferred first and then the corresponding data is expected. --@ ### Data Write: --@ With a data write request, the module transfers the **data** and the **address** ---@ to the two corresponding FIFO interfaces. +--@ to the corresponding FIFO interface. --@ ### Data Read: --@ With a data read request, the module transfers the **requested address** --@ to the FIFO interface. It then expects the corresponding data @@ -183,7 +183,7 @@ begin DataInFifo_DataAviable <= not DataInFifo_EmptyFlag; DataOutFifo_WriteEnable <= InterWriteEnableOut; - AddressOutFifo_WriteEnable <= InterRequestEnable or InterWriteEnableOut; + AddressOutFifo_WriteEnable <= InterRequestEnable; --@ Shifts the value from the `DEPP_AddressEnable` signal into the `EPP_AddressEnableShiftRegister` --@ for the rising/falling edge detection.