Add Logic Analyzer waveform captures to docs

Included new Logic Analyzer Captures section in README and created a corresponding markdown file with waveform images for various EPP cycles. This provides visual aids for better understanding the timing and behavior of EPP transactions.

README.md

@@ -24,6 +24,10 @@ The `DEPP.vhd` module is designed as an Enhanced Parallel Port (EPP) interface f
 
   ![Waveform of the EPP Data Read Cycle](docs/DEPP/wavedrom_91sO2.svg "EPP Data Read")
 
+### Logic Analyzer Captures
+
+The captures can be found in the [Logic Analyzer Captures](docs/Logic%20Analyzer%20Captures/Logic%20Analyzer%20Captures.md) directory.
+
 ## Port Definitions
 
 | Port Name        | Direction | Type        | Description                                        |

docs/Logic Analyzer Captures/Logic Analyzer Captures.md

@@ -0,0 +1,13 @@
+# Logic Analyzer Captures
+
+## Address Write Cycle
+
+![Waveform of the EPP Address Write Cycle](Address%20Write%20Cycle.webp "EPP Address Write")
+
+## Data Write Cycle
+
+![Waveform of the EPP Data Write Cycle](Data%20Write%20Cycle.webp "EPP Data Write")
+
+## Data Read Cycle
+
+![Waveform of the EPP Data Read Cycle](Data%20Read%20Cycle.webp "EPP Data Read")