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Add Logic Analyzer waveform captures to docs

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Included new Logic Analyzer Captures section in README and created a corresponding markdown file with waveform images for various EPP cycles. This provides visual aids for better understanding the timing and behavior of EPP transactions.
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0xMax42
2024-03-09 00:02:17 +01:00
parent bc7e848561
commit 4f5642709c
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README.md
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@@ -24,6 +24,10 @@ The `DEPP.vhd` module is designed as an Enhanced Parallel Port (EPP) interface f
![Waveform of the EPP Data Read Cycle](docs/DEPP/wavedrom_91sO2.svg "EPP Data Read") ![Waveform of the EPP Data Read Cycle](docs/DEPP/wavedrom_91sO2.svg "EPP Data Read")
### Logic Analyzer Captures
The captures can be found in the [Logic Analyzer Captures](docs/Logic%20Analyzer%20Captures/Logic%20Analyzer%20Captures.md) directory.
## Port Definitions ## Port Definitions
| Port Name | Direction | Type | Description | | Port Name | Direction | Type | Description |

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docs/Logic Analyzer Captures/Logic Analyzer Captures.md Normal file
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# Logic Analyzer Captures
## Address Write Cycle
![Waveform of the EPP Address Write Cycle](Address%20Write%20Cycle.webp "EPP Address Write")
## Data Write Cycle
![Waveform of the EPP Data Write Cycle](Data%20Write%20Cycle.webp "EPP Data Write")
## Data Read Cycle
![Waveform of the EPP Data Read Cycle](Data%20Read%20Cycle.webp "EPP Data Read")