HDL/Asynchronous-FIFO-AXI-Handshake
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MaxP ffbf5c4984 Add Gray counter implementation and testbench 
Introduces a synchronous Gray counter with configurable width, reset, enable, and look-ahead functionality. Implements binary-to-Gray and Gray-to-binary conversion functions. Includes a testbench for simulation and validation of the counter's behavior.
2025-04-16 17:30:22 +00:00
build @ 54949f43c0
Add build submodule configuration and initialize subproject
2025-04-01 09:18:05 +00:00
libs
Add Gray counter implementation and testbench
2025-04-16 17:30:22 +00:00
tests
Add Gray counter implementation and testbench
2025-04-16 17:30:22 +00:00
.gitignore
Add .gitignore to exclude locale files
2025-04-01 09:18:12 +00:00
.gitmodules
Add build submodule configuration and initialize subproject
2025-04-01 09:18:05 +00:00
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48 KiB
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VHDL 100%