MaxP
ffbf5c4984
Introduces a synchronous Gray counter with configurable width, reset, enable, and look-ahead functionality. Implements binary-to-Gray and Gray-to-binary conversion functions. Includes a testbench for simulation and validation of the counter's behavior.
46 lines
1.1 KiB
VHDL
46 lines
1.1 KiB
VHDL
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity GrayCounter_tb is
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end;
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architecture bench of GrayCounter_tb is
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-- Clock period
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constant clk_period : time := 10 ns;
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-- Generics
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constant G_Width : integer := 6;
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constant G_InitialValue : integer := 0;
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constant G_ResetValue : integer := 0;
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constant G_CountingDirection : string := "UP";
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constant G_LookAhead : integer := 1;
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-- Ports
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signal I_CLK : std_logic := '0';
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signal I_CE : std_logic := '1';
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signal I_RST : std_logic := '0';
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signal I_CountEnable : std_logic := '1';
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signal O_Value : std_logic_vector(G_Width - 1 downto 0);
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signal O_LookAheadValue : std_logic_vector(G_Width - 1 downto 0);
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begin
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GrayCounter_inst : entity work.GrayCounter
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generic map (
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G_Width => G_Width,
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G_InitialValue => G_InitialValue,
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G_ResetValue => G_ResetValue,
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G_CountingDirection => G_CountingDirection,
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G_LookAhead => G_LookAhead
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)
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port map (
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I_CLK => I_CLK,
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I_CE => I_CE,
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I_RST => I_RST,
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I_CountEnable => I_CountEnable,
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O_Value => O_Value,
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O_LAValue => O_LookAheadValue
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);
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I_CLK <= not I_CLK after clk_period/2;
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end; |