HDL/Asynchronous-FIFO-AXI-Handshake
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713f247229c998b6afb9efc54b5609f3f209ca37
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Max P 713f247229 .
2025-04-22 15:40:48 +00:00
build @ 54949f43c0
Add build submodule configuration and initialize subproject
2025-04-01 09:18:05 +00:00
libs
.
2025-04-22 15:40:48 +00:00
src
Add asynchronous FIFO with AXI-like interface
2025-04-16 17:30:42 +00:00
tests
Misc
2025-04-16 17:30:50 +00:00
.gitignore
Add .gitignore to exclude locale files
2025-04-01 09:18:12 +00:00
.gitmodules
Add build submodule configuration and initialize subproject
2025-04-01 09:18:05 +00:00
project.cfg
Misc
2025-04-16 17:30:50 +00:00
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48 KiB
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VHDL 100%