Asynchronous-FIFO-AXI-Handshake

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MaxP 57ad2aa377 Add asynchronous FIFO with AXI-like interface

Implements an asynchronous FIFO with independent read/write clocks and Gray code pointers for clock domain crossing. Refactors internal logic to use components like PipelineRegister and GrayCounter for improved synchronization and readability. Includes a testbench to validate functionality with data integrity checks.

Relates to version 1.1.2 updates.

2025-04-16 17:30:42 +00:00

build @ 54949f43c0

Add build submodule configuration and initialize subproject

2025-04-01 09:18:05 +00:00

libs

Add Gray counter implementation and testbench

2025-04-16 17:30:22 +00:00

src

Add asynchronous FIFO with AXI-like interface

2025-04-16 17:30:42 +00:00

tests

Add asynchronous FIFO with AXI-like interface