HDL/Asynchronous-FIFO-AXI-Handshake
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526ffaa790e50a2ccab47ac6b3342163644f4e80
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MaxP 526ffaa790 Misc
2025-04-16 17:30:50 +00:00
build @ 54949f43c0
Add build submodule configuration and initialize subproject
2025-04-01 09:18:05 +00:00
libs
Misc
2025-04-16 17:30:50 +00:00
src
Add asynchronous FIFO with AXI-like interface
2025-04-16 17:30:42 +00:00
tests
Misc
2025-04-16 17:30:50 +00:00
.gitignore
Add .gitignore to exclude locale files
2025-04-01 09:18:12 +00:00
.gitmodules
Add build submodule configuration and initialize subproject
2025-04-01 09:18:05 +00:00
project.cfg
Misc
2025-04-16 17:30:50 +00:00
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48 KiB
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VHDL 100%