AXI-HS-Scheduler/tb/Scheduler_tb.vhd

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
use std.env.stop;

entity Scheduler_tb is
end entity Scheduler_tb;

architecture Bench of Scheduler_tb is
    -- Clock period
    constant K_CLKPeriod : time := 10 ns;

    -- Generics
    constant G_DataWidth : integer := 32;
    -- Ports
    signal I_CLK : std_logic;
    signal I_CE : std_logic := '1';
    signal I_RST : std_logic := '0';
    signal I_P0_Valid : std_logic := '0';
    signal O_P0_Ready : std_logic := '0';
    signal I_P0_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
    signal I_P1_Valid : std_logic := '0';
    signal O_P1_Ready : std_logic := '0';
    signal I_P1_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
    signal I_P2_Valid : std_logic := '0';
    signal O_P2_Ready : std_logic := '0';
    signal I_P2_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
    signal I_P3_Valid : std_logic := '0';
    signal O_P3_Ready : std_logic := '0';
    signal I_P3_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
    signal O_Out_Valid : std_logic := '0';
    signal I_Out_Ready : std_logic := '0';
    signal O_Out_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
    signal O_Out_Address : std_logic_vector(1 downto 0) := (others => '0');

    signal TestDone : boolean := false;
begin

    ClockProc : process
    begin
        while TestDone = false loop
            I_CLK <= '0';
            wait for K_CLKPeriod / 2;
            I_CLK <= '1';
            wait for K_CLKPeriod / 2;
        end loop;

        I_CLK <= '0';
        stop(0);
        wait;
    end process;

    i_AXI_Handshaking_Scheduler_4 : entity work.AXI_Handshaking_Scheduler_4
        generic map(
            G_DataWidth => G_DataWidth
        )
        port map(
            I_CLK => I_CLK,
            I_CE => I_CE,
            I_RST => I_RST,
            I_P0_Valid => I_P0_Valid,
            O_P0_Ready => O_P0_Ready,
            I_P0_Data => I_P0_Data,
            I_P1_Valid => I_P1_Valid,
            O_P1_Ready => O_P1_Ready,
            I_P1_Data => I_P1_Data,
            I_P2_Valid => I_P2_Valid,
            O_P2_Ready => O_P2_Ready,
            I_P2_Data => I_P2_Data,
            I_P3_Valid => I_P3_Valid,
            O_P3_Ready => O_P3_Ready,
            I_P3_Data => I_P3_Data,
            O_Out_Valid => O_Out_Valid,
            I_Out_Ready => I_Out_Ready,
            O_Out_Data => O_Out_Data,
            O_Out_Address => O_Out_Address
        );

    ReceiverProc : process
        variable PacketCounter : integer := 0;
    begin
        I_Out_Ready <= '0';
        wait for 3 * K_CLKPeriod;

        loop
            -- Ein paar Takte Ready aktivieren
            I_Out_Ready <= '1';
            for i in 0 to 2 loop
                wait until rising_edge(I_CLK);
                if O_Out_Valid = '1' and I_Out_Ready = '1' then
                    report "Received packet #" & integer'image(PacketCounter) &
                        " from address " & integer'image(to_integer(unsigned(O_Out_Address))) &
                        " with data: " & integer'image(to_integer(unsigned(O_Out_Data)));

                    PacketCounter := PacketCounter + 1;
                end if;
            end loop;

            -- Pausephase
            -- I_Out_Ready <= '0';
            -- wait for 1 * K_CLKPeriod;
        end loop;
    end process;

    -- Sender 0: sendet 1 Paket
    Sender0Proc : process (I_CLK)
        constant K_MaxCount : integer := 280;
        variable V_Counter : integer := 0;
    begin
        if rising_edge(I_CLK) then
            if V_Counter < K_MaxCount then
                I_P0_Data <= std_logic_vector(to_unsigned(V_Counter, G_DataWidth));
                I_P0_Valid <= '1';
                if O_P0_Ready = '1' and I_P0_Valid = '1' then
                    report "Sender 0: Packet " & integer'image(V_Counter) & " sent with data: " & integer'image(to_integer(unsigned(I_P0_Data)));
                    V_Counter := V_Counter + 1;
                    if V_Counter = K_MaxCount then
                        I_P0_Valid <= '0';
                    end if;
                end if;
            else
                if V_Counter = K_MaxCount then
                    V_Counter := V_Counter + 1;
                    report "Sender 0: No more packets to send.";
                end if;
                I_P0_Valid <= '0';
            end if;
        end if;
    end process;

    -- Sender 1: sendet 1 Paket
    Sender1Proc : process (I_CLK)
        constant K_MaxCount : integer := 225;
        variable V_Counter : integer := 0;
    begin
        if rising_edge(I_CLK) then
            if V_Counter < K_MaxCount then
                I_P1_Data <= std_logic_vector(to_unsigned(V_Counter, G_DataWidth));
                I_P1_Valid <= '1';
                if O_P1_Ready = '1' and I_P1_Valid = '1' then
                    report "Sender 1: Packet " & integer'image(V_Counter) & " sent with data: " & integer'image(to_integer(unsigned(I_P1_Data)));
                    V_Counter := V_Counter + 1;
                    if V_Counter = K_MaxCount then
                        I_P1_Valid <= '0';
                    end if;
                end if;
            else
                if V_Counter = K_MaxCount then
                    V_Counter := V_Counter + 1;
                    report "Sender 1: No more packets to send.";
                end if;
                I_P1_Valid <= '0';
            end if;
        end if;
    end process;

    -- Sender 2: sendet 1 Paket
    Sender2Proc : process (I_CLK)
        constant K_MaxCount : integer := 665;
        variable V_Counter : integer := 0;
    begin
        if rising_edge(I_CLK) then
            if V_Counter < K_MaxCount then
                I_P2_Data <= std_logic_vector(to_unsigned(V_Counter, G_DataWidth));
                I_P2_Valid <= '1';
                if O_P2_Ready = '1' and I_P2_Valid = '1' then
                    report "Sender 2: Packet " & integer'image(V_Counter) & " sent with data: " & integer'image(to_integer(unsigned(I_P2_Data)));
                    V_Counter := V_Counter + 1;
                    if V_Counter = K_MaxCount then
                        I_P2_Valid <= '0';
                    end if;
                end if;
            else
                if V_Counter = K_MaxCount then
                    V_Counter := V_Counter + 1;
                    report "Sender 2: No more packets to send.";
                end if;
                I_P2_Valid <= '0';
            end if;
        end if;
    end process;

    -- Sender 3: sendet 1 Paket
    Sender3Proc : process (I_CLK)
        constant K_MaxCount : integer := 150;
        variable V_Counter : integer := 0;
    begin
        if rising_edge(I_CLK) then
            if V_Counter < K_MaxCount then
                I_P3_Data <= std_logic_vector(to_unsigned(V_Counter, G_DataWidth));
                I_P3_Valid <= '1';
                if O_P3_Ready = '1' and I_P3_Valid = '1' then
                    report "Sender 3: Packet " & integer'image(V_Counter) & " sent with data: " & integer'image(to_integer(unsigned(I_P3_Data)));
                    V_Counter := V_Counter + 1;
                    if V_Counter = K_MaxCount then
                        I_P3_Valid <= '0';
                    end if;
                end if;
            else
                if V_Counter = K_MaxCount then
                    V_Counter := V_Counter + 1;
                    report "Sender 3: No more packets to send.";
                end if;
                I_P3_Valid <= '0';
            end if;
        end if;
    end process;

end architecture;