310 lines
10 KiB
VHDL
310 lines
10 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.math_real.all;
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entity AXI_Handshaking_Scheduler_4 is
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generic (
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G_DataWidth : integer := 8;
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G_InBufferStages : integer := 1;
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G_OutBufferStages : integer := 1
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);
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port (
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--@ Clock signal; (**Rising edge** triggered)
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I_CLK : in std_logic;
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--@ Clock enable signal (**Active high**)
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I_CE : in std_logic;
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--@ Synchronous reset signal (**Active high**)
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I_RST : in std_logic;
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--@ @virtualbus P0 @dir in P0 interface
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I_P0_Valid : in std_logic := '0';
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O_P0_Ready : out std_logic := '0';
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I_P0_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
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--@ @end
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--@ @virtualbus P1 @dir in P1 interface
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I_P1_Valid : in std_logic := '0';
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O_P1_Ready : out std_logic := '0';
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I_P1_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
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--@ @end
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--@ @virtualbus P2 @dir in P2 interface
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I_P2_Valid : in std_logic := '0';
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O_P2_Ready : out std_logic := '0';
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I_P2_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
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--@ @end
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--@ @virtualbus P3 @dir in P3 interface
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I_P3_Valid : in std_logic := '0';
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O_P3_Ready : out std_logic := '0';
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I_P3_Data : in std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
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--@ @end
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--@ @virtualbus Out @dir out Output interface
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O_Out_Valid : out std_logic := '0';
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I_Out_Ready : in std_logic := '0';
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O_Out_Data : out std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
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O_Out_Address : out std_logic_vector(1 downto 0) := (others => '0')
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--@ @end
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);
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end entity AXI_Handshaking_Scheduler_4;
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architecture Rtl of AXI_Handshaking_Scheduler_4 is
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signal R_SelectRotator : unsigned(1 downto 0) := (others => '0');
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signal R1_SelectRotator : unsigned(1 downto 0) := (others => '0');
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signal C_Select : std_logic_vector(3 downto 0) := (others => '0');
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signal C_Code : std_logic_vector(1 downto 0) := (others => '0');
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signal R_Code : std_logic_vector(1 downto 0) := (others => '0');
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signal C_CodeUnrotated : std_logic_vector(1 downto 0) := (others => '0');
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signal S_P0_InBufferEnable : std_logic := '0';
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signal S_P0_Ready : std_logic := '0';
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signal S_P0_Valid : std_logic := '0';
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signal S_P0_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
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signal S_P1_InBufferEnable : std_logic := '0';
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signal S_P1_Ready : std_logic := '0';
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signal S_P1_Valid : std_logic := '0';
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signal S_P1_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
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signal S_P2_InBufferEnable : std_logic := '0';
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signal S_P2_Ready : std_logic := '0';
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signal S_P2_Valid : std_logic := '0';
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signal S_P2_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
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signal S_P3_InBufferEnable : std_logic := '0';
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signal S_P3_Ready : std_logic := '0';
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signal S_P3_Valid : std_logic := '0';
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signal S_P3_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
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signal S_OutBufferEnable : std_logic := '0';
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signal S_Out_Ready : std_logic := '0';
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signal S_Out_Valid : std_logic := '0';
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signal S_Out_Data : std_logic_vector(G_DataWidth - 1 downto 0) := (others => '0');
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signal S_Out_Address : std_logic_vector(1 downto 0) := (others => '0');
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begin
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I_P0_InBufferCtrl : entity work.PipelineController
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generic map(
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G_PipelineStages => G_InBufferStages
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)
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port map(
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I_CLK => I_CLK,
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I_CE => I_CE,
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I_RST => I_RST,
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O_Enable => S_P0_InBufferEnable,
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I_Valid => I_P0_Valid,
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O_Ready => O_P0_Ready,
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O_Valid => S_P0_Valid,
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I_Ready => S_P0_Ready
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);
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I_P0_InBuffer : entity work.PipelineRegister
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generic map(
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G_PipelineStages => G_InBufferStages,
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G_Width => G_DataWidth,
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G_RegisterBalancing => "forward"
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)
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port map(
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I_CLK => I_CLK,
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I_Enable => S_P0_InBufferEnable,
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I_Data => I_P0_Data,
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O_Data => S_P0_Data
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);
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I_P1_InBufferCtrl : entity work.PipelineController
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generic map(
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G_PipelineStages => G_InBufferStages
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)
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port map(
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I_CLK => I_CLK,
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I_CE => I_CE,
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I_RST => I_RST,
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O_Enable => S_P1_InBufferEnable,
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I_Valid => I_P1_Valid,
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O_Ready => O_P1_Ready,
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O_Valid => S_P1_Valid,
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I_Ready => S_P1_Ready
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);
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I_P1_InBuffer : entity work.PipelineRegister
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generic map(
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G_PipelineStages => G_InBufferStages,
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G_Width => G_DataWidth,
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G_RegisterBalancing => "forward"
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)
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port map(
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I_CLK => I_CLK,
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I_Enable => S_P1_InBufferEnable,
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I_Data => I_P1_Data,
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O_Data => S_P1_Data
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);
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I_P2_InBufferCtrl : entity work.PipelineController
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generic map(
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G_PipelineStages => G_InBufferStages
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)
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port map(
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I_CLK => I_CLK,
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I_CE => I_CE,
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I_RST => I_RST,
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O_Enable => S_P2_InBufferEnable,
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I_Valid => I_P2_Valid,
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O_Ready => O_P2_Ready,
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O_Valid => S_P2_Valid,
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I_Ready => S_P2_Ready
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);
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I_P2_InBuffer : entity work.PipelineRegister
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generic map(
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G_PipelineStages => G_InBufferStages,
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G_Width => G_DataWidth,
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G_RegisterBalancing => "forward"
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)
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port map(
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I_CLK => I_CLK,
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I_Enable => S_P2_InBufferEnable,
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I_Data => I_P2_Data,
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O_Data => S_P2_Data
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);
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I_P3_InBufferCtrl : entity work.PipelineController
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generic map(
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G_PipelineStages => G_InBufferStages
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)
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port map(
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I_CLK => I_CLK,
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I_CE => I_CE,
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I_RST => I_RST,
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O_Enable => S_P3_InBufferEnable,
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I_Valid => I_P3_Valid,
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O_Ready => O_P3_Ready,
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O_Valid => S_P3_Valid,
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I_Ready => S_P3_Ready
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);
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I_P3_InBuffer : entity work.PipelineRegister
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generic map(
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G_PipelineStages => G_InBufferStages,
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G_Width => G_DataWidth,
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G_RegisterBalancing => "forward"
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)
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port map(
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I_CLK => I_CLK,
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I_Enable => S_P3_InBufferEnable,
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I_Data => I_P3_Data,
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O_Data => S_P3_Data
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);
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I_PriorityEncoder_4 : entity work.PriorityEncoder_4
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port map(
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I_Select => C_Select,
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O_Code => C_Code
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);
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P_SelectMux : process (R_SelectRotator, S_P0_Valid, S_P1_Valid, S_P2_Valid, S_P3_Valid)
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begin
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case R_SelectRotator is when "00" =>
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C_Select <= S_P0_Valid & S_P1_Valid & S_P2_Valid & S_P3_Valid;
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when "01" =>
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C_Select <= S_P1_Valid & S_P2_Valid & S_P3_Valid & S_P0_Valid;
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when "10" =>
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C_Select <= S_P2_Valid & S_P3_Valid & S_P0_Valid & S_P1_Valid;
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when "11" =>
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C_Select <= S_P3_Valid & S_P0_Valid & S_P1_Valid & S_P2_Valid;
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when others =>
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C_Select <= (others => '-');
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end case;
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end process;
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P_CodeUnrotating : process (R_Code, R1_SelectRotator)
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begin
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C_CodeUnrotated <= std_logic_vector(unsigned(R_Code) + R1_SelectRotator);
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end process;
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P_OutMux : process (
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C_CodeUnrotated, S_P0_Data, S_P1_Data, S_P2_Data, S_P3_Data, S_P0_Valid, S_P1_Valid, S_P2_Valid, S_P3_Valid, S_Out_Ready)
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begin
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S_Out_Valid <= '0';
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S_P0_Ready <= '0';
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S_P1_Ready <= '0';
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S_P2_Ready <= '0';
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S_P3_Ready <= '0';
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S_Out_Data <= (others => '-');
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S_Out_Address <= C_CodeUnrotated;
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case C_CodeUnrotated is when "00" =>
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S_Out_Valid <= S_P0_Valid;
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S_P0_Ready <= S_Out_Ready;
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S_Out_Data <= S_P0_Data;
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when "01" =>
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S_Out_Valid <= S_P1_Valid;
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S_P1_Ready <= S_Out_Ready;
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S_Out_Data <= S_P1_Data;
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when "10" =>
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S_Out_Valid <= S_P2_Valid;
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S_P2_Ready <= S_Out_Ready;
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S_Out_Data <= S_P2_Data;
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when "11" =>
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S_Out_Valid <= S_P3_Valid;
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S_P3_Ready <= S_Out_Ready;
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S_Out_Data <= S_P3_Data;
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when others =>
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S_Out_Address <= (others => '-');
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end case;
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end process;
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P_SelectRotator : process (I_CLK)
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begin
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if rising_edge(I_CLK) then
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if I_CE = '1' then
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if I_RST = '1' then
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R_SelectRotator <= (others => '0');
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R1_SelectRotator <= (others => '0');
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R_Code <= (others => '0');
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else
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R1_SelectRotator <= R_SelectRotator;
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R_Code <= C_Code;
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if I_Out_Ready = '1' then
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R_SelectRotator <= unsigned(C_CodeUnrotated) + 1;
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end if;
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end if;
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end if;
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end if;
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end process P_SelectRotator;
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I_OutBufferCtrl : entity work.PipelineController
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generic map(
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G_PipelineStages => G_OutBufferStages
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)
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port map(
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I_CLK => I_CLK,
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I_CE => I_CE,
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I_RST => I_RST,
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O_Enable => S_OutBufferEnable,
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I_Valid => S_Out_Valid,
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O_Ready => S_Out_Ready,
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O_Valid => O_Out_Valid,
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I_Ready => I_Out_Ready
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);
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I_OutDataBuffer : entity work.PipelineRegister
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generic map(
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G_PipelineStages => G_OutBufferStages,
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G_Width => G_DataWidth,
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G_RegisterBalancing => "backward"
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)
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port map(
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I_CLK => I_CLK,
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I_Enable => S_OutBufferEnable,
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I_Data => S_Out_Data,
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O_Data => O_Out_Data
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);
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I_OutAddressBuffer : entity work.PipelineRegister
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generic map(
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G_PipelineStages => G_OutBufferStages,
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G_Width => 2,
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G_RegisterBalancing => "backward"
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)
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port map(
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I_CLK => I_CLK,
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I_Enable => S_OutBufferEnable,
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I_Data => S_Out_Address,
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O_Data => O_Out_Address
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);
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end architecture;
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