Max P
ba8cc2ef94
Extends tool configuration to include ISim options by adding a new field to the model and example configuration file. Supports specifying ISim arguments for enhanced simulation workflows.
61 lines
800 B
YAML
61 lines
800 B
YAML
name: VGA
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topmodule: VGA_Test
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target_device: xc3s1200e-4-fg320
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xilinx_path: /opt/Xilinx/14.7/ISE_DS/ISE
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sources:
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vhdl:
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- path: vhdl/*.vhd
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library: work
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verilog: []
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dependencies:
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- git: "https://git.0xmax42.io/maxp/Asynchronous-FIFO-AXI-Handshake.git"
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rev: "hdlbuild"
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testbenches:
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vhdl:
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- path: vhdltests/*.vhd
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library: work
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verilog: []
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constraints: vhdl/VGA_test.ucf
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build:
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build_dir: working
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report_dir: reports
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copy_target_dir: output
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# Tool Optionen
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tool_options:
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common:
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- "-intstyle"
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- "xflow"
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xst:
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- "-opt_mode Speed"
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- "-opt_level 2"
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ngdbuild: []
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map:
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- "-detail"
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par: []
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bitgen:
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- "-g"
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- "StartupClk:JtagClk"
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trace:
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- "-v"
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- "3"
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- "-n"
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- "3"
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fuse: []
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isim:
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- "-gui" |