* Update Makefile for ISIM test enhancements and version bump
**This changes based on [Wayne Booth](https://github.com/WayneBooth/Xilinx-ISE-Makefile/tree/master)
Introduced support for running and building individual ISIM testbenches to streamline testing of VHDL and Verilog modules. The update modifies the Makefile to include options for a graphical user interface and command extraction from testbench files. Simplified the `test` target into `buildtest` and `runtest` targets for better modularity and clearer separation of the build and execution phases. Also incremented the Makefile version to reflect these significant changes to the testing workflow.
* Update Makefile to version 1.1.1
* Updated Makefile for consistent build output paths and dynamic project references
Enhanced the Makefile to use a centralized `BUILD_DIR` variable for executable paths, increasing consistency across the build process. Adjusted the project reference generation to dynamically pair test files with their respective libraries, ensuring a more accurate and maintainable build configuration. This change streamlines the build workflow and mitigates potential errors due to path mismatches or hard-coded library links.
* Add copy feature
* Add a comprehensive sample configuration file for the project
This commit adds a sample configuration file for the project. It includes main settings such as the project name, target device, and path to the Xilinx ISE installation. It also provides options for source files, test files, ISE executable settings, and programmer settings. This sample configuration file serves as a template for users to customize their project settings.
