Remove detailed Xilinx ISE Makefile documentation from README.md
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# Xilinx ISE Makefile
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**Todo**
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Tired of clicking around in Xilinx ISE? Run your builds from the command line!
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## Forked from..
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The original project is located at [Xilinx-ISE-Makefile](https://github.com/duskwuff/Xilinx-ISE-Makefile) and was created by [duskwuff](github.com/duskwuff/).
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Many thanks for the good work!
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## Requirements
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- Xilinx ISE, ideally 14.7 (the final version)
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Works great on Linux. Windows Subsystem for Linux is tested and works well.
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- GNU (or compatible?) Make
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Install this through Cygwin on Windows.
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## Creating a project
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To start building a project, you will need to create a file `project.cfg` in
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the top level of your project. This file is a text file sourced by Make, so
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it consists of `KEY = value` pairs. It must define at least the following keys:
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- `PROJECT`
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The name of the project, used as a name for certain intermediate files, and
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as the default name for the top-level module and constraints file.
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- `TARGET_PART`
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The full part-speed-package identifier for the Xilinx part to be targeted,
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e.g. `xc6slx9-2-tqg144`.
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- `XILINX`
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The path to the appropriate binaries directory of the target Xilinx ISE
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install, e.g.
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`/cygdrive/c/Xilinx/14.7/ISE_DS/ISE`
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or
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`/opt/Xilinx/14.7/ISE_DS/ISE`
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for typical installs.
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- `VSOURCE` and/or `VHDSOURCE`
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The space-separated names of all Verilog and/or VHDL source files to be
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used in the project.
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You can define these on multiple lines using `+=`, e.g.
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VSOURCE += foo.v
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VSOURCE += bar.v
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You can also add a library name to the source file, e.g.
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VSOURCE += my_lib:foo.v
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VSOURCE += my_lib:bar.v
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The default library name is `work`.
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A simple `project.cfg` may thus resemble:
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PROJECT = example
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TARGET_PART = xc6slx9-2-cpg196
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XILINX = /cygdrive/c/Xilinx/14.7/ISE_DS/ISE/bin/nt64
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VSOURCE = example.v
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A number of other keys can be set in the project configuration, including:
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- `XILINX_PLATFORM`
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The Xilinx name for the platform to build for, e.g. `nt64` or `lin`.
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`nt64` is used by default for Windows systems, and `lin64` for Linux
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systems, so you only need to set this if you explicitly need to use the
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32-bit version of the tools for some reason.
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- `TOPLEVEL`
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The name of the top-level module to be used in the project.
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(Defaults to `$PROJECT`.)
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- `CONSTRAINTS`
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The name of the constraints file (`.ucf`) to be used for the project.
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(Defaults to `$PROJECT.ucf`.)
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- `COMMON_OPTS`
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Extra command-line options to be passed to all ISE executables. Defaults to
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`-intstyle xflow`.
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- `XST_OPTS`, `NGDBUILD_OPTS`, `MAP_OPTS`, `PAR_OPTS`, `BITGEN_OPTS`,
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`TRACE_OPTS`, `FUSE_OPTS`
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Extra command-line options to be passed to the corresponding ISE tools.
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Defaults is:
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```
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XST_OPTS ?=
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NGDBUILD_OPTS ?=
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MAP_OPTS ?= -detail
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PAR_OPTS ?=
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BITGEN_OPTS ?=
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TRACE_OPTS ?= -v 3 -n 3
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FUSE_OPTS ?= -incremental
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```
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Note that `XST_OPTS` will not appear on the command line during
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compilation, as the XST options are embedded in a script file.
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`MAP_OPTS` and `PAR_OPTS` can be set to `-mt 2` to use multithreading,
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which may speed up compilation of large designs.
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`BITGEN_OPTS` can be set to `-g Compress` to apply bitstream compression.
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- `PROGRAMMER`
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The name of the programmer to be used for `make prog`. Currently supported
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values are:
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- `impact`
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Uses Xilinx iMPACT for programming, using a batch file named
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`impact.cmd` by default. The iMPACT command line may be overridden by
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setting `IMPACT_OPTS`.
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A typical batch file may resemble:
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setMode -bscan
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setCable -p auto
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addDevice -p 1 -file build/projectname.bit
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program -p 1
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quit
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- `digilent`
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Uses the Digilent JTAG utility for programming, which must be installed
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separately. The name of the board must be set as `DJTG_DEVICE`; the
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path to the djtgcfg executable can be set as `DJTG_EXE`, and the index
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of the device can be set as `DJTG_INDEX`. You can set the flash index
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with `DJTG_FLASH_INDEX`.
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- `xc3sprog`
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Uses the xc3sprog utility for programming, which must also be installed
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separately. The cable name must be set as `XC3SPROG_CABLE`; additional
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options can be set as `XC3SPROG_OPTS`.
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- `PROGRAMMER_PRE`
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A command to be run before programming. This can be used to use `sudo` or
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`yes` to confirm programming.
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## Targets
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The Xilinx ISE Makefile implements the following targets:
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- `make default` (or just `make`)
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Builds the bitstream.
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- `make clean`
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Removes the build directory.
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- `make prog`
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Writes the bitstream to a target device. Requires some additional
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configuration; see below for details.
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- `make flash`
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Writes the bitstream to a flash device.
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**This is currently only for digilent implemented.**
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## Console output
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After a successful build, you will find the paths to the generated **reports** on the console. E.g.:
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```
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============ Reports.. ===========
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==== Synthesis Summary Report ====
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./build/Example.srp
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======= Map Summary Report =======
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./build/Example.map.mrp
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======= PAR Summary Report =======
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./build/Example.par
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===== Pinout Summary Report ======
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./build/Example_pad.txt
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```
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## Unimplemented features
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The following features are not currently implemented. (Pull requests are
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encouraged!)
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- Generation of SPI or other unusual programming files
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- CPLD synthesis
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- Synthesis tools other than XST
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- Display and/or handling of warnings and errors from `build/_xmsgs`
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- Running unit tests
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- Anything else (open an issue?)
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## License
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To the extent possible under law, the author(s) have dedicated all copyright
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and related and neighboring rights to this software to the public domain
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worldwide. This software is distributed without any warranty.
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See LICENSE.md for details.
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