diff --git a/Makefile b/Makefile
index 7a38cfb..7d774a2 100644
--- a/Makefile
+++ b/Makefile
@@ -35,30 +35,32 @@ ifndef TARGET_PART
     $(error TARGET_PART must be defined)
 endif
 
-TOPLEVEL        ?= $(PROJECT)
-CONSTRAINTS     ?= $(PROJECT).ucf
-BITFILE         ?= build/$(PROJECT).bit
+TOPLEVEL         ?= $(PROJECT)
+CONSTRAINTS      ?= $(PROJECT).ucf
+BITFILE          ?= build/$(PROJECT).bit
+ 
+COMMON_OPTS      ?= -intstyle xflow
+XST_OPTS         ?=
+NGDBUILD_OPTS    ?=
+MAP_OPTS         ?= -detail 
+PAR_OPTS         ?=
+BITGEN_OPTS      ?=
+TRACE_OPTS       ?= -v 3 -n 3
+FUSE_OPTS        ?= -incremental
+ 
+PROGRAMMER       ?= none
+PROGRAMMER_PRE   ?=
+ 
+IMPACT_OPTS      ?= -batch impact.cmd
+ 
+DJTG_EXE         ?= djtgcfg
+DJTG_DEVICE      ?= DJTG_DEVICE-NOT-SET
+DJTG_INDEX       ?= 0
+DJTG_FLASH_INDEX ?= 1
 
-COMMON_OPTS     ?= -intstyle xflow
-XST_OPTS        ?=
-NGDBUILD_OPTS   ?=
-MAP_OPTS        ?=
-PAR_OPTS        ?= -detail 
-BITGEN_OPTS     ?=
-TRACE_OPTS      ?= -v 3 -n 3
-FUSE_OPTS       ?= -incremental
-
-PROGRAMMER      ?= none
-
-IMPACT_OPTS     ?= -batch impact.cmd
-
-DJTG_EXE        ?= djtgcfg
-DJTG_DEVICE     ?= DJTG_DEVICE-NOT-SET
-DJTG_INDEX      ?= 0
-
-XC3SPROG_EXE    ?= xc3sprog
-XC3SPROG_CABLE  ?= none
-XC3SPROG_OPTS   ?=
+XC3SPROG_EXE     ?= xc3sprog
+XC3SPROG_CABLE   ?= none
+XC3SPROG_OPTS    ?=
 
 
 ###########################################################################
@@ -209,17 +211,17 @@ isimgui: build/isim_$(TB)$(EXE)
 
 ifeq ($(PROGRAMMER), impact)
 prog: $(BITFILE)
-	sudo $(XILINX)/bin/$(XILINX_PLATFORM)/impact $(IMPACT_OPTS)
+	$(PROGRAMMER_PRE) $(XILINX)/bin/$(XILINX_PLATFORM)/impact $(IMPACT_OPTS)
 endif
 
 ifeq ($(PROGRAMMER), digilent)
 prog: $(BITFILE)
-	yes Y | sudo $(DJTG_EXE) prog -d $(DJTG_DEVICE) -i $(DJTG_INDEX) -f $(BITFILE)
+	$(PROGRAMMER_PRE) $(DJTG_EXE) prog -d $(DJTG_DEVICE) -i $(DJTG_INDEX) -f $(BITFILE)
 endif
 
 ifeq ($(PROGRAMMER), xc3sprog)
 prog: $(BITFILE)
-	sudo $(XC3SPROG_EXE) -c $(XC3SPROG_CABLE) $(XC3SPROG_OPTS) $(BITFILE)
+	$(PROGRAMMER_PRE) $(XC3SPROG_EXE) -c $(XC3SPROG_CABLE) $(XC3SPROG_OPTS) $(BITFILE)
 endif
 
 ifeq ($(PROGRAMMER), none)
@@ -233,7 +235,7 @@ endif
 
 ifeq ($(PROGRAMMER), digilent)
 flash: $(BITFILE)
-	yes Y | sudo $(DJTG_EXE) prog -d $(DJTG_DEVICE) -i $(DJTG_FLASH_INDEX) -f $(BITFILE)
+	$(PROGRAMMER_PRE) $(DJTG_EXE) prog -d $(DJTG_DEVICE) -i $(DJTG_FLASH_INDEX) -f $(BITFILE)
 endif
 
 ###########################################################################
diff --git a/README.md b/README.md
index 7433831..1a756bd 100644
--- a/README.md
+++ b/README.md
@@ -12,9 +12,11 @@ Many thanks for the good work!
 
 - Xilinx ISE, ideally 14.7 (the final version)
 
-- GNU (or compatible?) Make \
-  Install this through Cygwin on Windows \
-  or on Linux. (Windows Subsystem for Linux is tested)
+  Works great on Linux. Windows Subsystem for Linux is tested and works well.
+
+- GNU (or compatible?) Make
+
+  Install this through Cygwin on Windows.
 
 ## Creating a project
 
@@ -51,6 +53,13 @@ it consists of `KEY = value` pairs. It must define at least the following keys:
       VSOURCE += foo.v
       VSOURCE += bar.v
 
+  You can also add a library name to the source file, e.g.
+
+      VSOURCE += my_lib:foo.v
+      VSOURCE += my_lib:bar.v
+
+  The default library name is `work`.
+
 A simple `project.cfg` may thus resemble:
 
     PROJECT = example
@@ -87,8 +96,19 @@ A number of other keys can be set in the project configuration, including:
 - `XST_OPTS`, `NGDBUILD_OPTS`, `MAP_OPTS`, `PAR_OPTS`, `BITGEN_OPTS`,
   `TRACE_OPTS`, `FUSE_OPTS`
 
-  Extra command-line options to be passed to the corresponding ISE tools. All
-  default to empty.
+  Extra command-line options to be passed to the corresponding ISE tools.
+
+  Defaults is:
+
+  ```
+  XST_OPTS        ?=
+  NGDBUILD_OPTS   ?=
+  MAP_OPTS        ?= -detail
+  PAR_OPTS        ?=
+  BITGEN_OPTS     ?=
+  TRACE_OPTS      ?= -v 3 -n 3
+  FUSE_OPTS       ?= -incremental
+  ```
 
   Note that `XST_OPTS` will not appear on the command line during
   compilation, as the XST options are embedded in a script file.
@@ -122,7 +142,8 @@ A number of other keys can be set in the project configuration, including:
     Uses the Digilent JTAG utility for programming, which must be installed
     separately. The name of the board must be set as `DJTG_DEVICE`; the
     path to the djtgcfg executable can be set as `DJTG_EXE`, and the index
-    of the device can be set as `DJTG_INDEX`.
+    of the device can be set as `DJTG_INDEX`. You can set the flash index
+    with `DJTG_FLASH_INDEX`.
 
   - `xc3sprog`
 
@@ -130,6 +151,11 @@ A number of other keys can be set in the project configuration, including:
     separately. The cable name must be set as `XC3SPROG_CABLE`; additional
     options can be set as `XC3SPROG_OPTS`.
 
+- `PROGRAMMER_PRE`
+
+  A command to be run before programming. This can be used to use `sudo` or
+  `yes` to confirm programming.
+
 ## Targets
 
 The Xilinx ISE Makefile implements the following targets:
@@ -147,9 +173,31 @@ The Xilinx ISE Makefile implements the following targets:
   Writes the bitstream to a target device. Requires some additional
   configuration; see below for details.
 
-## Running unit tests
+- `make flash`
 
-is a work in progress.
+  Writes the bitstream to a flash device.
+  **This is currently only for digilent implemented.**
+
+## Console output
+
+After a successful build, you will find the paths to the generated **reports** on the console. E.g.:
+
+```
+============ Reports.. ===========
+
+==== Synthesis Summary Report ====
+ ./build/Example.srp
+
+======= Map Summary Report =======
+ ./build/Example.map.mrp
+
+======= PAR Summary Report =======
+ ./build/Example.par
+
+===== Pinout Summary Report ======
+ ./build/Example_pad.txt
+
+```
 
 ## Unimplemented features
 
@@ -164,6 +212,8 @@ encouraged!)
 
 - Display and/or handling of warnings and errors from `build/_xmsgs`
 
+- Running unit tests
+
 - Anything else (open an issue?)
 
 ## License