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Update Makefile for ISIM test enhancements and version bump

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**This changes based on [Wayne Booth](https://github.com/WayneBooth/Xilinx-ISE-Makefile/tree/master)

Introduced support for running and building individual ISIM testbenches to streamline testing of VHDL and Verilog modules. The update modifies the Makefile to include options for a graphical user interface and command extraction from testbench files. Simplified the `test` target into `buildtest` and `runtest` targets for better modularity and clearer separation of the build and execution phases. Also incremented the Makefile version to reflect these significant changes to the testing workflow.
This commit is contained in:
0xMax42
2024-03-10 15:31:22 +01:00
parent d7eebb6517
commit 11d446ec3e
1 changed files with 34 additions and 13 deletions
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47
Makefile
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@@ -12,7 +12,7 @@
# Version
###########################################################################
Makefile_Version := 1.0.3
Makefile_Version := 1.1.0
$(info ISE Makefile Version: $(Makefile_Version))
###########################################################################
@@ -51,6 +51,9 @@ BITGEN_OPTS ?=
TRACE_OPTS ?= -v 3 -n 3
FUSE_OPTS ?= -incremental
ISIM_OPTS ?= -gui
ISIM_CMD ?= vcd dumpfile $@.vcd\nvcd dumpvars -m /UUT\nrun all\nvcd dumpflush\nquit
PROGRAMMER ?= none
PROGRAMMER_PRE ?=
@@ -114,6 +117,25 @@ $(eval $(call process_sources,$(VHDSOURCE),VHD_LIBS,VHD_PATHS))
# Run the function for Verilog sources
$(eval $(call process_sources,$(VSOURCE),V_LIBS,V_PATHS))
## Tests
# Initialize the libs and paths variables for VHDL and Verilog testbenches
VHD_TEST_PATHS ?=
VHD_TEST_LIBS ?=
V_TEST_PATHS ?=
V_TEST_LIBS ?=
# Run the function for VHDL tests
$(eval $(call process_sources,$(VHDTEST),VHD_TEST_LIBS,VHD_TEST_PATHS))
# Run the function for Verilog tests
$(eval $(call process_sources,$(VTEST),V_TEST_LIBS,V_TEST_PATHS))
# Get the test names..
TEST_PATHS = $(foreach file,$(V_TEST_PATHS) $(VHD_TEST_PATHS),$(basename $(file)))
TEST_NAMES = $(foreach path,$(TEST_PATHS),$(notdir $(path)))
TEST_EXES = $(foreach test,$(TEST_NAMES),build/isim_$(test)$(EXE))
###########################################################################
# Default build
###########################################################################
@@ -189,24 +211,23 @@ trace: ../project.cfg $(BITFILE)
@echo "\e[1;97m===== Timing Summary Report ======\e[m"
@echo "\e[1;35m ./$(BUILD_DIR)/$(PROJECT).twr\e[m\n"
test: $(TEST_EXES)
test: buildtest runtest
$(BUILD_DIR)/isim_%$(EXE): $(V_PATHS) $(VHD_PATHS) $(BUILD_DIR)/$(PROJECT)_sim.prj $(VTEST) $(VHDTEST)
runtest: ${TEST_NAMES}
${TEST_NAMES}:
@grep --no-filename --no-messages 'ISIM:' $@.{v,vhd} | cut -d: -f2 > build/isim_$@.cmd
@echo "$(ISIM_CMD)" >> build/isim_$@.cmd
cd build ; ./isim_$@$(EXE) $(ISIM_OPTS) -tclbatch isim_$@.cmd ;
buildtest: ${TEST_EXES}
$(BUILD_DIR)/isim_%$(EXE): build/$(PROJECT)_sim.prj $(VSOURCE) $(VHDSOURCE) ${V_TEST_PATHS} $(VHD_TEST_PATHS)
$(call RUN,fuse) $(COMMON_OPTS) $(FUSE_OPTS) \
-prj $(PROJECT)_sim.prj \
-o isim_$*$(EXE) \
work.$* work.glbl
isim: $(BUILD_DIR)/isim_$(TB)$(EXE)
@grep --no-filename --no-messages 'ISIM:' $(TB).{v,vhd} | cut -d: -f2 > $(BUILD_DIR)/isim_$(TB).cmd
@echo "run all" >> $(BUILD_DIR)/isim_$(TB).cmd
cd $(BUILD_DIR) ; ./isim_$(TB)$(EXE) -tclbatch isim_$(TB).cmd
isimgui: $(BUILD_DIR)/isim_$(TB)$(EXE)
@grep --no-filename --no-messages 'ISIM:' $(TB).{v,vhd} | cut -d: -f2 > $(BUILD_DIR)/isim_$(TB).cmd
@echo "run all" >> $(BUILD_DIR)/isim_$(TB).cmd
cd $(BUILD_DIR) ; ./isim_$(TB)$(EXE) -gui -tclbatch isim_$(TB).cmd
###########################################################################
# Programming