MaxP
daa1abf477
Replaces CalcPipeline with HorizontalSpritePipeline for improved readability and maintainability. Introduces a structured pipeline architecture with enhanced visibility checks, ROM access efficiency, and modular design principles. Provides better handling of non-visible pixels and adheres to AXI-like handshake standards.
302 lines
12 KiB
VHDL
302 lines
12 KiB
VHDL
----------------------------------------------------------------------------------
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--@ - Name: **HorizontalSpritePipeline**
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--@ - Version: 0.0.1
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--@ - Author: _0xMax42 ([Blog](0xMax42.io))_
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--@ - License: [MIT](LICENSE)
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--@
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--@ ## Description
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--@ This pipeline calculates whether a sprite is visible at a given horizontal
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--@ scanline position (X coordinate), and if so, outputs the corresponding pixel
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--@ address and color data.
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--@
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--@ The operation is fully pipelined and includes the following steps:
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--@ - Latching of sprite index, offset, and X positions
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--@ - Calculation of the horizontal offset between request and sprite position
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--@ - Visibility check against the maximum sprite width
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--@ - ROM address generation for the sprite pixel
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--@ - Forwarding of pixel data to the output pipeline
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--@
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--@ Non-visible pixels (outside the horizontal sprite bounds) are filtered out
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--@ before any ROM access occurs. The pipeline uses fully synchronous logic
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--@ and AXI-like handshake signals across all bus interfaces.
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--@
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--@ ## History
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--@ - 0.0.1 (2025-04-20) Initial version
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----------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.math_real.all;
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entity HorizontalSpritePipeline is
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generic (
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--@ Width of the sprite index (Base address) register
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G_Index_Width : integer := 5;
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--@ Width of the sprite offset (Line address) register
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G_Offset_Width : integer := 8;
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--@ Width of the X position (Row) register
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G_X_Width : integer := 10;
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--@ Width of the pixel data from rom
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G_Rom_Width : integer := 8;
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--@ Width of the pixel data output
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G_Pixel_Width : integer := 8;
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--@ Horizontal width of a sprite in pixels
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G_SpriteMaxWidth : integer := 16
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);
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port (
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--@ Clock; (**Rising edge** triggered)
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I_CLK : in std_logic;
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--@ Clock Enable; (**Synchronous**, **Active high**)
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I_CE : in std_logic;
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--@ Reset; (**Synchronous**, **Active high**)
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I_RST : in std_logic;
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--@ @virtualbus Operation @dir In Operation input bus
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--@ AXI like valid; (**Synchronous**, **Active high**)
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I_OP_Valid : in std_logic;
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--@ AXI like ready; (**Synchronous**, **Active high**)
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O_OP_Ready : out std_logic;
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--@ Index address
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I_OP_Index : in std_logic_vector(G_Index_Width - 1 downto 0);
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--@ Offset address
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I_OP_Offset : in std_logic_vector(G_Offset_Width - 1 downto 0);
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--@ X position of the request
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I_OP_X_Request : in std_logic_vector(G_X_Width - 1 downto 0);
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--@ X position of the sprite
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I_OP_X_Sprite : in std_logic_vector(G_X_Width - 1 downto 0);
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--@ @end
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--@ @virtualbus Rom-Address @dir Out Request rom data bus
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--@ AXI like valid; (**Synchronous**, **Active high**)
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O_Rom_Valid : out std_logic;
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--@ AXI like ready; (**Synchronous**, **Active high**)
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I_Rom_Ready : in std_logic;
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--@ Rom address
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O_Rom_Address : out std_logic_vector(G_Index_Width + G_Offset_Width - 1 downto 0);
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--@ @end
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--@ @virtualbus Rom-Data @dir In Rom data bus
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--@ AXI like valid; (**Synchronous**, **Active high**)
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I_Rom_Valid : in std_logic;
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--@ AXI like ready; (**Synchronous**, **Active high**)
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O_Rom_Ready : out std_logic;
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--@ Rom data
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I_Rom_Data : in std_logic_vector(G_Rom_Width - 1 downto 0);
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--@ @end
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--@ @virtualbus Pixel-Data @dir Out Pixel data output bus
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--@ AXI like valid; (**Synchronous**, **Active high**)
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O_Pixel_Valid : out std_logic;
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--@ AXI like ready; (**Synchronous**, **Active high**)
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I_Pixel_Ready : in std_logic;
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--@ Pixel data
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O_Pixel_Data : out std_logic_vector(G_Pixel_Width - 1 downto 0)
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--@ @end
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);
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end entity HorizontalSpritePipeline;
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architecture RTL of HorizontalSpritePipeline is
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--@ Register enable for the horizontal sprite pipeline
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signal O_HSpritePipelineCtrl_Enable : std_logic := '0';
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--@ Ready in signal for the **output** of the horizontal sprite pipeline
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signal I_HSpritePipeline_Ready : std_logic := '0';
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--@ Valid out signal for the **output** of the horizontal sprite pipeline
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signal O_HSpritePipeline_Valid : std_logic := '0';
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--@ Register for the `I_OP_Index` signal (Pipeline stage 1/2)
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signal R_Index : std_logic_vector(G_Index_Width - 1 downto 0) := (others => '0');
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--@ Register for the `I_OP_Offset` signal (Pipeline stage 1/2)
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signal R_Offset : std_logic_vector(G_Offset_Width - 1 downto 0) := (others => '0');
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--@ Register for the `I_OP_X_Request` signal (Pipeline stage 1)
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signal R_X_Request : std_logic_vector(G_X_Width - 1 downto 0) := (others => '0');
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--@ Register for the `I_OP_X_Sprite` signal (Pipeline stage 1)
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signal R_X_Sprite : std_logic_vector(G_X_Width - 1 downto 0) := (others => '0');
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--@ Calculated sprite X offset (Between pipeline stage 1 and 2)
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signal C_Sprite_X_Offset : std_logic_vector(G_X_Width - 1 downto 0) := (others => '0');
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--@ Register for the calculated sprite X offset (Pipeline stage 2)
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signal R_Sprite_X_Offset : std_logic_vector(G_X_Width - 1 downto 0) := (others => '0');
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--@ Calculated address for the ROM (Between pipeline stage 2 and 3)
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signal C_Address : std_logic_vector(G_Index_Width + G_Offset_Width - 1 downto 0) := (others => '0');
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--@ Register for the calculated address for the ROM (Pipeline stage 3)
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signal R_Address : std_logic_vector(G_Index_Width + G_Offset_Width - 1 downto 0) := (others => '0');
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--@ Calculated visibility signal (Between pipeline stage 2 and 3)
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signal C_X_Visible : std_logic := '0';
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--@ Register for the calculated visibility signal (Pipeline stage 3)
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signal R_X_Visible : std_logic := '0';
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--@ Valid signal for the ROM request (From pipeline stage 3 to 4; after filtering)
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signal I_RomRequest_Valid : std_logic := '0';
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--@ Ready signal for the ROM request (From pipeline stage 3 to 4; after filtering)
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signal O_RomRequest_Ready : std_logic := '0';
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begin
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INST_HSpritePipelineCtrl : entity work.PipelineController
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generic map(
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G_PipelineStages => 3
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)
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port map(
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I_CLK => I_CLK,
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I_CE => I_CE,
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O_Enable => O_HSpritePipelineCtrl_Enable,
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I_Valid => I_OP_Valid,
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O_Ready => O_OP_Ready,
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O_Valid => O_HSpritePipeline_Valid,
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I_Ready => I_HSpritePipeline_Ready
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);
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INST_HSpritePipeline_Index : entity work.PipelineRegister
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generic map(
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G_PipelineStages => 2,
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G_Width => G_Index_Width,
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G_RegisterBalancing => "forward"
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)
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port map(
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I_CLK => I_CLK,
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I_Enable => O_HSpritePipelineCtrl_Enable,
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I_Data => I_OP_Index,
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O_Data => R_Index
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);
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INST_HSpritePipeline_Offset : entity work.PipelineRegister
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generic map(
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G_PipelineStages => 2,
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G_Width => G_Offset_Width,
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G_RegisterBalancing => "forward"
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)
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port map(
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I_CLK => I_CLK,
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I_Enable => O_HSpritePipelineCtrl_Enable,
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I_Data => I_OP_Offset,
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O_Data => R_Offset
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);
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INST_HSpritePipeline_Request : entity work.PipelineRegister
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generic map(
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G_PipelineStages => 1,
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G_Width => G_X_Width,
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G_RegisterBalancing => "forward"
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)
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port map(
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I_CLK => I_CLK,
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I_Enable => O_HSpritePipelineCtrl_Enable,
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I_Data => I_OP_X_Request,
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O_Data => R_X_Request
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);
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INST_HSpritePipeline_X_Sprite : entity work.PipelineRegister
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generic map(
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G_PipelineStages => 1,
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G_Width => G_X_Width,
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G_RegisterBalancing => "forward"
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)
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port map(
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I_CLK => I_CLK,
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I_Enable => O_HSpritePipelineCtrl_Enable,
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I_Data => I_OP_X_Sprite,
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O_Data => R_X_Sprite
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);
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C_Sprite_X_Offset <= std_logic_vector(
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unsigned(R_X_Request) - unsigned(R_X_Sprite)
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);
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INST_HSpritePipeline_X_Offset : entity work.PipelineRegister
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generic map(
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G_PipelineStages => 1,
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G_Width => G_X_Width,
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G_RegisterBalancing => "yes"
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)
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port map(
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I_CLK => I_CLK,
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I_Enable => O_HSpritePipelineCtrl_Enable,
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I_Data => C_Sprite_X_Offset,
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O_Data => R_Sprite_X_Offset
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);
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C_Address <= R_Index & std_logic_vector(
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unsigned(R_Offset) + unsigned(R_Sprite_X_Offset(G_Offset_Width - 1 downto 0))
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);
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C_X_Visible <= '1' when unsigned(R_Sprite_X_Offset) < G_SpriteMaxWidth else
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'0';
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INST_HSpritePipeline_Address : entity work.PipelineRegister
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generic map(
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G_PipelineStages => 1,
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G_Width => G_Index_Width + G_Offset_Width,
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G_RegisterBalancing => "backward"
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)
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port map(
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I_CLK => I_CLK,
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I_Enable => O_HSpritePipelineCtrl_Enable,
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I_Data => C_Address,
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O_Data => R_Address
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);
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INST_HSpritePipeline_X_Visible : entity work.PipelineRegister
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generic map(
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G_PipelineStages => 1,
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G_Width => 1,
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G_RegisterBalancing => "backward"
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)
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port map(
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I_CLK => I_CLK,
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I_Enable => O_HSpritePipelineCtrl_Enable,
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I_Data(0) => C_X_Visible,
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O_Data(0) => R_X_Visible
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);
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INST_DropUnvisibleRequests : entity work.PipelineFilter
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generic map(
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G_MaskWidth => 1,
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G_Mask => "1",
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G_MaskMode => "not_equal"
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)
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port map(
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I_Match(0) => R_X_Visible,
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I_Valid => O_HSpritePipeline_Valid,
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O_Ready => I_HSpritePipeline_Ready,
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O_Valid => I_RomRequest_Valid,
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I_Ready => O_RomRequest_Ready
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);
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INST_RomRequestBuffer : entity work.PipelineStage
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generic map(
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G_PipelineStages => 1,
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G_D0_Width => G_Index_Width + G_Offset_Width
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)
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port map(
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I_CLK => I_CLK,
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I_CE => I_CE,
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I_RST => I_RST,
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I_Valid => I_RomRequest_Valid,
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O_Ready => O_RomRequest_Ready,
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I_Data_0 => R_Address,
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O_Valid => O_Rom_Valid,
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I_Ready => I_Rom_Ready,
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O_Data_0 => O_Rom_Address
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);
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INST_PixelDataBuffer : entity work.PipelineStage
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generic map(
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G_PipelineStages => 1,
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G_D0_Width => G_Pixel_Width
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)
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port map(
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I_CLK => I_CLK,
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I_CE => I_CE,
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I_RST => I_RST,
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I_Valid => I_Rom_Valid,
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O_Ready => O_Rom_Ready,
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I_Data_0 => I_Rom_Data,
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O_Valid => O_Pixel_Valid,
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I_Ready => I_Pixel_Ready,
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O_Data_0 => O_Pixel_Data
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);
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end architecture;
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