195 lines
7.4 KiB
VHDL
195 lines
7.4 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use std.env.stop;
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use work.OPCodes.all;
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entity SpriteChannel_tb is
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end entity SpriteChannel_tb;
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architecture Testbench of SpriteChannel_tb is
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function to_hex(v : std_logic_vector) return string is
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variable h : string(1 to 8); -- Maximal 8 Hex-Zeichen
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variable u : unsigned(v'range) := unsigned(v);
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begin
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for i in h'range loop
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exit when i > (v'length + 3) / 4;
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case to_integer(u((v'length - 1) - (i - 1) * 4 downto v'length - i * 4)) is
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when 0 => h(i) := '0';
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when 1 => h(i) := '1';
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when 2 => h(i) := '2';
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when 3 => h(i) := '3';
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when 4 => h(i) := '4';
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when 5 => h(i) := '5';
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when 6 => h(i) := '6';
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when 7 => h(i) := '7';
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when 8 => h(i) := '8';
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when 9 => h(i) := '9';
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when 10 => h(i) := 'A';
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when 11 => h(i) := 'B';
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when 12 => h(i) := 'C';
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when 13 => h(i) := 'D';
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when 14 => h(i) := 'E';
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when 15 => h(i) := 'F';
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when others => h(i) := '?';
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end case;
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end loop;
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return h(1 to (v'length + 3) / 4);
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end;
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-- Clock period
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constant K_CLKPeriod : time := 10 ns;
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-- Generics
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constant G_OPCodeData_Width : integer := 10;
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constant G_Index_Width : integer := 5;
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constant G_Offset_Width : integer := 8;
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constant G_X_Width : integer := 10;
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constant G_Y_Width : integer := 10;
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constant G_Sprite_Height : integer := 16;
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constant G_Sprite_Width : integer := 16;
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-- Ports
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signal I_CLK : std_logic;
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signal I_CE : std_logic := '1';
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signal I_RST : std_logic := '0';
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signal I_OP_Valid : std_logic := '0';
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signal O_OP_Ready : std_logic := '0';
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signal I_OP_Code : std_logic_vector(3 downto 0) := (others => '0');
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signal I_OP_Data : std_logic_vector(G_OPCodeData_Width - 1 downto 0) := (others => '0');
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signal O_Pixel_Valid : std_logic := '0';
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signal I_Pixel_Ready : std_logic := '0';
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signal O_Pixel_Data : std_logic_vector(7 downto 0) := (others => '0');
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signal TestDone : boolean := false;
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-- Testdaten für Befehle
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type T_Command is record
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OP_Code : std_logic_vector(3 downto 0);
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OP_Data : std_logic_vector(G_OPCodeData_Width - 1 downto 0);
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end record;
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type T_CommandArray is array (natural range <>) of T_Command;
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constant CommandSequence : T_CommandArray := (
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(OP_Code => K_OP_NEWLINE, OP_Data => "0000000100"),
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(OP_Code => K_OP_REQ_ROW_DATA, OP_Data => "0000000000"),
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(OP_Code => K_OP_REQ_ROW_DATA, OP_Data => "0000000001"),
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(OP_Code => K_OP_REQ_ROW_DATA, OP_Data => "0000000010"),
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(OP_Code => K_OP_REQ_ROW_DATA, OP_Data => "0000000011"),
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(OP_Code => K_OP_REQ_ROW_DATA, OP_Data => "0000000100"),
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(OP_Code => K_OP_REQ_ROW_DATA, OP_Data => "0000000101"),
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(OP_Code => K_OP_REQ_ROW_DATA, OP_Data => "0000000110"),
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(OP_Code => K_OP_REQ_ROW_DATA, OP_Data => "0000000111"),
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(OP_Code => K_OP_REQ_ROW_DATA, OP_Data => "0000001000"),
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(OP_Code => K_OP_REQ_ROW_DATA, OP_Data => "0000001001"),
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(OP_Code => K_OP_REQ_ROW_DATA, OP_Data => "0000001010"),
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(OP_Code => K_OP_REQ_ROW_DATA, OP_Data => "0000001011"),
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(OP_Code => K_OP_REQ_ROW_DATA, OP_Data => "0000001100"),
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(OP_Code => K_OP_REQ_ROW_DATA, OP_Data => "0000001101"),
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(OP_Code => K_OP_REQ_ROW_DATA, OP_Data => "0000001110"),
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(OP_Code => K_OP_REQ_ROW_DATA, OP_Data => "0000001111"),
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(OP_Code => K_OP_REQ_ROW_DATA, OP_Data => "0000010000"),
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(OP_Code => K_OP_REQ_ROW_DATA, OP_Data => "0000010001")
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);
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begin
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ClockProc : process
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begin
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while TestDone = false loop
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I_CLK <= '0';
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wait for K_CLKPeriod / 2;
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I_CLK <= '1';
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wait for K_CLKPeriod / 2;
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end loop;
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I_CLK <= '0';
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stop(0);
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wait;
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end process;
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StimulusProc : process
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variable i : integer := 0;
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begin
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-- Initialisierung
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I_RST <= '1';
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wait for K_CLKPeriod * 2;
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I_RST <= '0';
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wait for K_CLKPeriod * 2;
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-- Befehle senden
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for i in CommandSequence'range loop
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-- Warten, bis das Modul bereit ist
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wait until rising_edge(I_CLK);
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while O_OP_Ready /= '1' loop
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wait until rising_edge(I_CLK);
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end loop;
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-- Befehl setzen
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I_OP_Code <= CommandSequence(i).OP_Code;
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I_OP_Data <= CommandSequence(i).OP_Data;
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I_OP_Valid <= '1';
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-- Einen Takt warten
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wait until rising_edge(I_CLK);
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I_OP_Valid <= '0';
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-- Warten, bis der Befehl verarbeitet wurde
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while O_OP_Ready /= '1' loop
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wait until rising_edge(I_CLK);
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end loop;
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-- Optional: Ergebnisse prüfen (falls relevant)
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report "Befehl " & integer'image(i) & " erfolgreich gesendet." severity note;
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end loop;
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wait for K_CLKPeriod * 10;
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-- Test abgeschlossen
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report "Alle Befehle erfolgreich gesendet." severity note;
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TestDone <= true;
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wait;
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end process;
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AXIReceiverProc : process
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variable V_PacketCount : integer := 0;
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begin
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-- Initialisierung
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I_Pixel_Ready <= '1'; -- Signalisiert, dass Daten empfangen werden können
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while TestDone = false loop
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-- Warten, bis gültige Daten anliegen
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wait until rising_edge(I_CLK);
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if O_Pixel_Valid = '1' then
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report "Empfangenes Paket #" & integer'image(V_PacketCount) &
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" (hex): " & to_hex(O_Pixel_Data)
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severity note;
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V_PacketCount := V_PacketCount + 1;
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end if;
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end loop;
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wait;
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end process;
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i_SpriteChannel : entity work.SpriteChannel
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generic map(
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G_OPCodeData_Width => G_OPCodeData_Width,
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G_Index_Width => G_Index_Width,
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G_Offset_Width => G_Offset_Width,
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G_X_Width => G_X_Width,
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G_Y_Width => G_Y_Width,
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G_Sprite_Height => G_Sprite_Height,
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G_Sprite_Width => G_Sprite_Width
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)
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port map(
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I_CLK => I_CLK,
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I_CE => I_CE,
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I_RST => I_RST,
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I_OP_Valid => I_OP_Valid,
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O_OP_Ready => O_OP_Ready,
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I_OP_Code => I_OP_Code,
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I_OP_Data => I_OP_Data,
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O_Pixel_Valid => O_Pixel_Valid,
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I_Pixel_Ready => I_Pixel_Ready,
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O_Pixel_Data => O_Pixel_Data
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);
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end architecture;
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