222 lines
11 KiB
VHDL
222 lines
11 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use work.OPCodes.all;
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use std.env.stop;
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entity OPDecoder_tb is
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end entity OPDecoder_tb;
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architecture bench of OPDecoder_tb is
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-- Clock period
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constant K_CLKPeriod : time := 10 ns;
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-- Generics
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constant G_OPCodeData_Width : integer := 10;
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constant G_ROM_DataWidth : integer := 16;
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constant G_Index_Width : integer := 6;
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constant G_Offset_Width : integer := 4;
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constant G_LineData_Width : integer := 16;
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constant G_X_Width : integer := 10;
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constant G_Y_Width : integer := 10;
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constant G_Sprite_Height : integer := 16;
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constant G_PipelineStages : integer := 2;
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-- Ports
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signal I_CLK : std_logic;
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signal I_CE : std_logic;
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signal I_RST : std_logic;
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signal I_OP_Valid : std_logic := '0';
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signal O_OP_Ready : std_logic := '0';
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signal I_OP_Code : std_logic_vector(3 downto 0) := (others => '0');
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signal I_OP_Data : std_logic_vector(G_OPCodeData_Width - 1 downto 0) := (others => '0');
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signal O_Register_Index_WE : std_logic := '0';
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signal O_Register_Index : std_logic_vector(G_Index_Width - 1 downto 0) := (others => '0');
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signal O_Register_Offset_WE : std_logic := '0';
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signal O_Register_Offset : std_logic_vector(G_Offset_Width - 1 downto 0) := (others => '0');
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signal O_Register_X_We : std_logic := '0';
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signal O_Register_X : std_logic_vector(G_X_Width - 1 downto 0) := (others => '0');
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signal O_Register_Y_WE : std_logic := '0';
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signal O_Register_Y : std_logic_vector(G_Y_Width - 1 downto 0) := (others => '0');
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signal O_Register_CachedLineData_WE : std_logic := '0';
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signal O_Register_CachedLineData : std_logic_vector(G_LineData_Width - 1 downto 0) := (others => '0');
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signal O_Register_CacheValid_WE : std_logic := '0';
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signal O_Register_CacheValid : std_logic := '0';
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signal I_YHitCheck_Ready : std_logic := '0';
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signal O_YHitCheck_Valid : std_logic := '0';
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signal O_YHitCheck_YToCheck : std_logic_vector(G_Y_Width - 1 downto 0) := (others => '0');
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signal O_YHitCheck_Ready : std_logic := '0';
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signal I_YHitCheck_Valid : std_logic := '0';
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signal I_YHitCheck_IsVisible : std_logic := '0';
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signal I_YHitCheck_Offset : std_logic_vector(G_Offset_Width - 1 downto 0) := (others => '0');
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signal O_Rom_Valid : std_logic := '0';
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signal I_Rom_Ready : std_logic := '0';
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signal I_Rom_Valid : std_logic := '0';
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signal O_Rom_Ready : std_logic := '0';
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signal I_Rom_Data : std_logic_vector(G_ROM_DataWidth - 1 downto 0) := (others => '0');
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signal O_CalcPipeline_Valid : std_logic := '0';
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signal I_CalcPipeline_Ready : std_logic := '0';
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signal O_CalcPipeline_X : std_logic_vector(G_X_Width - 1 downto 0) := (others => '0');
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signal R1, R2 : std_logic := '0';
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signal TestDone : boolean := false;
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begin
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ClockProc : process
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begin
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while TestDone = false loop
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I_CLK <= '0';
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wait for K_CLKPeriod / 2;
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I_CLK <= '1';
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wait for K_CLKPeriod / 2;
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end loop;
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I_CLK <= '0';
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stop(0);
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wait;
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end process;
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i_OPDecoder : entity work.OPDecoder
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generic map(
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G_OPCodeData_Width => G_OPCodeData_Width,
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G_ROM_DataWidth => G_ROM_DataWidth,
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G_Index_Width => G_Index_Width,
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G_Offset_Width => G_Offset_Width,
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G_LineData_Width => G_LineData_Width,
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G_X_Width => G_X_Width,
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G_Y_Width => G_Y_Width
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)
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port map(
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I_CLK => I_CLK,
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I_CE => I_CE,
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I_RST => I_RST,
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I_OPDecoder_Valid => I_OP_Valid,
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O_OPDecoder_Ready => O_OP_Ready,
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I_OPDecoder_Code => I_OP_Code,
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I_OPDecoder_Data => I_OP_Data,
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O_RFile_Wr_Index_WE => O_Register_Index_WE,
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O_RFile_Wr_Index => O_Register_Index,
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O_RFile_Wr_Offset_WE => O_Register_Offset_WE,
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O_RFile_Wr_Offset => O_Register_Offset,
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O_RFile_Wr_X_We => O_Register_X_We,
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O_RFile_Wr_X => O_Register_X,
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O_RFile_Wr_Y_WE => O_Register_Y_WE,
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O_RFile_Wr_Y => O_Register_Y,
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O_Register_CachedLineData_WE => O_Register_CachedLineData_WE,
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O_Register_CachedLineData => O_Register_CachedLineData,
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O_Register_CacheValid_WE => O_Register_CacheValid_WE,
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O_Register_CacheValid => O_Register_CacheValid,
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I_VSpritePipeline_Ready => I_YHitCheck_Ready,
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O_VSpritePipeline_Valid => O_YHitCheck_Valid,
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O_VSpritePipeline_YToCheck => O_YHitCheck_YToCheck,
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O_VSpritePipeline_Ready => O_YHitCheck_Ready,
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I_VSpritePipeline_Valid => I_YHitCheck_Valid,
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I_VSpritePipeline_IsVisible => I_YHitCheck_IsVisible,
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I_VSpritePipeline_Offset => I_YHitCheck_Offset,
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O_Rom_Valid => O_Rom_Valid,
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I_Rom_Ready => I_Rom_Ready,
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I_Rom_Valid => I_Rom_Valid,
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O_Rom_Ready => O_Rom_Ready,
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I_Rom_Data => I_Rom_Data,
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O_HSpritePipeline_Valid => O_CalcPipeline_Valid,
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I_HSpritePipeline_Ready => I_CalcPipeline_Ready,
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O_HSpritePipeline_X_Request => O_CalcPipeline_X
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);
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I_CalcPipeline_Ready <= O_CalcPipeline_Valid;
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i_YHitCheck : entity work.VerticalSpritePipeline
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generic map(
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G_Y_Width => G_Y_Width,
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G_Sprite_Height => G_Sprite_Height,
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G_Offset_Width => G_Offset_Width,
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G_PipelineStages => G_PipelineStages
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)
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port map(
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I_CLK => I_CLK,
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I_CE => I_CE,
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O_VSpritePipeline_OP_Ready => I_YHitCheck_Ready,
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I_VSpritePipeline_OP_Valid => O_YHitCheck_Valid,
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I_VSpritePipeline_OP_Y_Request => O_YHitCheck_YToCheck,
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I_VSpritePipeline_OP_Y_Sprite => "0000000000",
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I_VSpritePipeline_Ready => O_YHitCheck_Ready,
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O_VSpritePipeline_Valid => I_YHitCheck_Valid,
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O_VSpritePipeline_IsVisible => I_YHitCheck_IsVisible,
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O_VSpritePipeline_Offset => I_YHitCheck_Offset
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);
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StimulusProc : process
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type T_OpTest is record
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Code : std_logic_vector(3 downto 0);
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Data : std_logic_vector(G_OPCodeData_Width - 1 downto 0);
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Name : string(1 to 20);
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end record;
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type T_OpTestArray is array (natural range <>) of T_OpTest;
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constant TestCases : T_OpTestArray := (
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0 => (K_OP_NOP, (others => '0'), "NOP "),
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1 => (K_OP_SET_ID, std_logic_vector(to_unsigned(2, G_OPCodeData_Width)), "SET_ID "),
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2 => (K_OP_SET_X, std_logic_vector(to_unsigned(3, G_OPCodeData_Width)), "SET_X "),
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3 => (K_OP_SET_Y, std_logic_vector(to_unsigned(4, G_OPCodeData_Width)), "SET_Y "),
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4 => (K_OP_CLEAR_ALL, (others => '1'), "CLEAR_ALL "),
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6 => (K_OP_REQ_ROW_DATA, std_logic_vector(to_unsigned(5, G_OPCodeData_Width)), "REQ_ROW_DATA "),
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5 => (K_OP_NEWLINE, std_logic_vector(to_unsigned(1, G_Y_Width)), "NEWLINE ")
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);
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variable i : integer;
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begin
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-- Init
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I_RST <= '1';
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I_CE <= '1';
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wait for K_CLKPeriod * 2;
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I_RST <= '0';
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wait for K_CLKPeriod * 2;
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for i in TestCases'range loop
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-- Warte auf Ready
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wait until rising_edge(I_CLK);
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while O_OP_Ready /= '1' loop
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wait until rising_edge(I_CLK);
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end loop;
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I_OP_Code <= TestCases(i).Code;
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I_OP_Data <= TestCases(i).Data;
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I_OP_Valid <= '1';
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wait until rising_edge(I_CLK);
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I_OP_Valid <= '0';
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-- Einfach ein bisschen warten, bis Modul durch ist
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-- wait for K_CLKPeriod * 5;
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report "Opcode-Test: " & TestCases(i).Name & " abgeschlossen." severity note;
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end loop;
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report "Alle OPCodes getestet." severity note;
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TestDone <= true;
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wait;
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end process;
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-- ROM Simulation: immer gültig, gibt X"FFFF" zurück
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RomProcess : process (I_CLK)
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begin
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if rising_edge(I_CLK) then
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if I_CE = '1' then
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-- Standard: nichts tun
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I_Rom_Valid <= '0';
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I_Rom_Data <= (others => '0');
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-- Prüfen, ob Decoder Daten anfordert
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if O_Rom_Valid = '1' then
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I_Rom_Valid <= '1';
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I_Rom_Data <= (others => '1'); -- z.B. X"FFFF"
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end if;
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end if;
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end if;
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end process;
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-- ROM ist immer bereit
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I_Rom_Ready <= '1';
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end architecture;
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