## Main settings.. ##

# Project name
# @remark The name of the project is used as default name for the top module and the ucf file
PROJECT = 

# Target device
# @example xc3s1200e-4-fg320 | xc5vlx50t-1-ff1136
TARGET_PART = 

# Path to the Xilinx ISE installation
XILINX = /opt/Xilinx/14.7/ISE_DS/ISE

# Optional the name of the top module (default is the project name)
# TOPLEVEL = 

# Optional the path/name of the ucf file (default is the project name)
# CONSTRAINTS = 

# Optional a target to copy the bit file to (make copy)
# COPY_TARGET_DIR = 

## ## ## ## ## ## ## ##
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## Source files settings.. ##
# The source files to be compiled
# @example `VSOURCE += src/main.v` (add a single Verilog file per line)
# @example `VHDSOURCE += src/main.vhd` (add a single VHDL file per line)


## Test files settings.. ##
# The testbench files to be compiled
# @example `VTEST += tests/main_tb.v` (add a single Verilog testbench file per line)
# @example `VHDTEST += tests/main_tb.vhd` (add a single VHDL testbench file per line)


## ## ## ## ## ## ## ##
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## ISE executable settings.. ##

# General command line options to be passed to all ISE executables (default is `-intstyle xflow`)
# COMMON_OPTS = 

# Options for the XST synthesizer
# @example -register_balancing (yes|no)
# @example -opt_mode (speed|area)
# @example -opt_level (1|2)
XST_OPTS = 

# Options for the NGDBuild tool
# NGDBUILD_OPTS =

# Options for the MAP tool
# @example -mt 2 (multi-threading with 2 threads)
# @example -cm speed (speed optimization)
# @example -ol high
# @example -detail
# @example -timing
MAP_OPTS = 

# Options for the PAR tool
# @example -mt 2 (multi-threading with 2 threads)
# @example -ol high
PAR_OPTS = 

# Options for the BitGen tool
# @example -g Compress (compress bitstream)
# @example -g StartupClk:Cclk (specify the startup clock to onboard clock)
# @example -g StartupClk:JtagClk (specify the startup clock to JTAG clock)
BITGEN_OPTS = -g StartupClk:JtagClk

# Options for the Trace tool
# TRACE_OPTS = 

# Options for the Fuse tool
# FUSE_OPTS = 

# Options for the ISim simulator
# @example -gui (start the simulator in GUI mode)
# ISIM_OPTS =

# Options for the ISim batch file
# @example vcd dumpfile $@.vcd \n vcd dumpvars -m /UUT \n run all \n vcd dumpflush \n quit
# ISIM_CMD =

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## Programmer settings.. ##

# The programmer to use
# @example impact | digilent | xc3sprog
# @remark impact is the default Xilinx programmer and you must create a impact.cmd file in the root directory..
PROGRAMMER = 

## Digilent JTAG cable settings

# @remark Use the `djtgcfg enum` command to list all available devices
# DJTG_DEVICE = DOnbUsb

# The index of the JTAG device for the `prog` target
# DJTG_INDEX = 0

# The index of the flash device for the `flash` target
# DJTG_FLASH_INDEX = 1

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