HDL/SpriteChannel
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Add pipeline stages parameter to PipelineRegister instances and refactor C_Offset calculation
All checks were successful
Manuelles Build mit ISE / build (push) Successful in 38s
Details

Browse Source
This commit is contained in:
0xMax42
2025-04-25 11:38:28 +00:00
parent a9ddd1a12d
commit 7e78e62b47
1 changed files with 29 additions and 12 deletions
Download Patch File Download Diff File Expand all files Collapse all files

41
src/VerticalSpritePipeline.vhd
View File

@@ -82,7 +82,8 @@ begin
INST0_VSpritePipeline_Y_Sprite : entity work.PipelineRegister
generic map(
G_Width => G_Y_Width
G_PipelineStages => 1,
G_Width => G_Y_Width
)
port map(
I_CLK => I_CLK,
@@ -93,7 +94,8 @@ begin
INST0_VSpritePipeline_Y_Request : entity work.PipelineRegister
generic map(
G_Width => G_Y_Width
G_PipelineStages => 1,
G_Width => G_Y_Width
)
port map(
I_CLK => I_CLK,
@@ -109,7 +111,8 @@ begin
INST_VSpritePipeline_Y_Bottom_Sprite : entity work.PipelineRegister
generic map(
G_Width => G_Y_Width
G_PipelineStages => 1,
G_Width => G_Y_Width
)
port map(
I_CLK => I_CLK,
@@ -120,7 +123,8 @@ begin
INST1_VSpritePipeline_Y_Sprite : entity work.PipelineRegister
generic map(
G_Width => G_Y_Width
G_PipelineStages => 1,
G_Width => G_Y_Width
)
port map(
I_CLK => I_CLK,
@@ -131,7 +135,8 @@ begin
INST1_VSpritePipeline_Y_Request : entity work.PipelineRegister
generic map(
G_Width => G_Y_Width
G_PipelineStages => 1,
G_Width => G_Y_Width
)
port map(
I_CLK => I_CLK,
@@ -147,15 +152,26 @@ begin
) else '0';
--@ Calculate the offset address of the sprite
C_Offset <= std_logic_vector(
to_unsigned(
K_SPRITE_ROW_OFFSETS(to_integer(unsigned(R1_Y_Request) - unsigned(R1_Y_Sprite))),
C_Offset'length)
);
process (R1_Y_Request, R1_Y_Sprite)
variable V_SPRITE_ROW_OFFSETS_Address : integer := 0;
begin
V_SPRITE_ROW_OFFSETS_Address := to_integer(unsigned(R1_Y_Request) - unsigned(R1_Y_Sprite));
if V_SPRITE_ROW_OFFSETS_Address > 0 and V_SPRITE_ROW_OFFSETS_Address < G_Sprite_Height then
C_Offset <= std_logic_vector(
to_unsigned(
K_SPRITE_ROW_OFFSETS(V_SPRITE_ROW_OFFSETS_Address),
C_Offset'length)
);
else
C_Offset <= (others => '0');
end if;
end process;
INST_IsVisible_OutputRegister : entity work.PipelineRegister
generic map(
G_Width => 1
G_PipelineStages => 1,
G_Width => 1
)
port map(
I_CLK => I_CLK,
@@ -166,7 +182,8 @@ begin
INST_Offset_OutputRegister : entity work.PipelineRegister
generic map(
G_Width => G_Offset_Width
G_PipelineStages => 1,
G_Width => G_Offset_Width
)
port map(
I_CLK => I_CLK,