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This commit is contained in:
0xMax42
2025-04-22 15:23:15 +00:00
parent 7888d608ae
commit 73a436eb40
14 changed files with 1038 additions and 415 deletions
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82
test/OPDecoder_tb.vhd
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@@ -9,17 +9,17 @@ end entity OPDecoder_tb;
architecture bench of OPDecoder_tb is
-- Clock period
constant K_CLKPeriod : time := 10 ns;
constant K_CLKPeriod : time := 10 ns;
-- Generics
constant G_OPCodeData_Width : integer := 10;
constant G_ROM_DataWidth : integer := 16;
constant G_Index_Width : integer := 6;
constant G_Offset_Width : integer := 4;
constant G_LineData_Width : integer := 16;
constant G_X_Width : integer := 10;
constant G_Y_Width : integer := 10;
constant G_Sprite_Height : integer := 16;
constant G_PipelineStages : integer := 2;
constant G_OPCodeData_Width : integer := 10;
constant G_ROM_DataWidth : integer := 16;
constant G_Index_Width : integer := 6;
constant G_Offset_Width : integer := 4;
constant G_LineData_Width : integer := 16;
constant G_X_Width : integer := 10;
constant G_Y_Width : integer := 10;
constant G_Sprite_Height : integer := 16;
constant G_PipelineStages : integer := 2;
-- Ports
signal I_CLK : std_logic;
@@ -57,9 +57,9 @@ architecture bench of OPDecoder_tb is
signal I_CalcPipeline_Ready : std_logic := '0';
signal O_CalcPipeline_X : std_logic_vector(G_X_Width - 1 downto 0) := (others => '0');
signal R1, R2 : std_logic := '0';
signal R1, R2 : std_logic := '0';
signal TestDone : boolean := false;
signal TestDone : boolean := false;
begin
ClockProc : process
@@ -90,29 +90,29 @@ begin
I_CLK => I_CLK,
I_CE => I_CE,
I_RST => I_RST,
I_OP_Valid => I_OP_Valid,
O_OP_Ready => O_OP_Ready,
I_OP_Code => I_OP_Code,
I_OP_Data => I_OP_Data,
O_Register_Index_WE => O_Register_Index_WE,
O_Register_Index => O_Register_Index,
O_Register_Offset_WE => O_Register_Offset_WE,
O_Register_Offset => O_Register_Offset,
O_Register_X_We => O_Register_X_We,
O_Register_X => O_Register_X,
O_Register_Y_WE => O_Register_Y_WE,
O_Register_Y => O_Register_Y,
I_OPDecoder_Valid => I_OP_Valid,
O_OPDecoder_Ready => O_OP_Ready,
I_OPDecoder_Code => I_OP_Code,
I_OPDecoder_Data => I_OP_Data,
O_RFile_Wr_Index_WE => O_Register_Index_WE,
O_RFile_Wr_Index => O_Register_Index,
O_RFile_Wr_Offset_WE => O_Register_Offset_WE,
O_RFile_Wr_Offset => O_Register_Offset,
O_RFile_Wr_X_We => O_Register_X_We,
O_RFile_Wr_X => O_Register_X,
O_RFile_Wr_Y_WE => O_Register_Y_WE,
O_RFile_Wr_Y => O_Register_Y,
O_Register_CachedLineData_WE => O_Register_CachedLineData_WE,
O_Register_CachedLineData => O_Register_CachedLineData,
O_Register_CacheValid_WE => O_Register_CacheValid_WE,
O_Register_CacheValid => O_Register_CacheValid,
I_YHitCheck_Ready => I_YHitCheck_Ready,
O_YHitCheck_Valid => O_YHitCheck_Valid,
O_YHitCheck_YToCheck => O_YHitCheck_YToCheck,
O_YHitCheck_Ready => O_YHitCheck_Ready,
I_YHitCheck_Valid => I_YHitCheck_Valid,
I_YHitCheck_IsVisible => I_YHitCheck_IsVisible,
I_YHitCheck_Offset => I_YHitCheck_Offset,
I_VSpritePipeline_Ready => I_YHitCheck_Ready,
O_VSpritePipeline_Valid => O_YHitCheck_Valid,
O_VSpritePipeline_YToCheck => O_YHitCheck_YToCheck,
O_VSpritePipeline_Ready => O_YHitCheck_Ready,
I_VSpritePipeline_Valid => I_YHitCheck_Valid,
I_VSpritePipeline_IsVisible => I_YHitCheck_IsVisible,
I_VSpritePipeline_Offset => I_YHitCheck_Offset,
O_Rom_Valid => O_Rom_Valid,
I_Rom_Ready => I_Rom_Ready,
I_Rom_Valid => I_Rom_Valid,
@@ -133,16 +133,16 @@ begin
G_PipelineStages => G_PipelineStages
)
port map(
I_CLK => I_CLK,
I_CE => I_CE,
O_Ready => I_YHitCheck_Ready,
I_Valid => O_YHitCheck_Valid,
I_YToCheck => O_YHitCheck_YToCheck,
I_Y => "0000000000",
I_Ready => O_YHitCheck_Ready,
O_Valid => I_YHitCheck_Valid,
O_IsVisible => I_YHitCheck_IsVisible,
O_Offset => I_YHitCheck_Offset
I_CLK => I_CLK,
I_CE => I_CE,
O_VSpritePipeline_OP_Ready => I_YHitCheck_Ready,
I_VSpritePipeline_OP_Valid => O_YHitCheck_Valid,
I_VSpritePipeline_OP_Y_Request => O_YHitCheck_YToCheck,
I_VSpritePipeline_OP_Y_Sprite => "0000000000",
I_VSpritePipeline_Ready => O_YHitCheck_Ready,
O_VSpritePipeline_Valid => I_YHitCheck_Valid,
O_VSpritePipeline_IsVisible => I_YHitCheck_IsVisible,
O_VSpritePipeline_Offset => I_YHitCheck_Offset
);
StimulusProc : process