Add testbench and configuration files for SpriteChannel and YHitCheck modules

Not functional yet

test/RegisterFile_tb.vhd.bak

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+
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+use std.env.stop;
+
+entity SpriteChannel_RegisterFile_tb is
+end;
+
+architecture bench of SpriteChannel_RegisterFile_tb is
+    -- Clock period
+    constant K_CLKPeriod : time := 10 ns;
+
+    -- Generics
+    constant G_SpriteIDWidth : integer := 10;
+    constant G_SpriteLineWidth : integer := 16;
+    constant G_XWidth : integer := 10;
+    constant G_YWidth : integer := 10;
+
+    -- Ports
+    signal I_CLK : std_logic;
+    signal I_CE : std_logic;
+    signal I_RST : std_logic;
+    signal I_SpriteID_WE : std_logic;
+    signal I_SpriteID : std_logic_vector(G_SpriteIDWidth - 1 downto 0);
+    signal I_X_WE : std_logic;
+    signal I_X : std_logic_vector(G_XWidth - 1 downto 0);
+    signal I_Y_WE : std_logic;
+    signal I_Y : std_logic_vector(G_YWidth - 1 downto 0);
+    signal I_SpriteLine_WE : std_logic;
+    signal I_SpriteLine : std_logic_vector(G_SpriteLineWidth - 1 downto 0);
+    signal I_SpriteLineValid_WE : std_logic;
+    signal I_SpriteLineValid : std_logic;
+    signal O_SpriteID : std_logic_vector(G_SpriteIDWidth - 1 downto 0);
+    signal O_X : std_logic_vector(G_XWidth - 1 downto 0);
+    signal O_Y : std_logic_vector(G_YWidth - 1 downto 0);
+    signal O_SpriteLine : std_logic_vector(G_SpriteLineWidth - 1 downto 0);
+    signal O_SpriteLineValid : std_logic;
+
+    -- Test control signals
+    signal TestDone : boolean := false;
+
+    type T_TestCase is record
+        SpriteID : integer;
+        X : integer;
+        Y : integer;
+        SpriteLine : integer;
+        SpriteLineValid : std_logic;
+    end record;
+
+    type T_TestArray is array (natural range <>) of T_TestCase;
+
+    constant TestValues : T_TestArray := (
+        (SpriteID => 5, X => 100, Y => 200, SpriteLine => 1234, SpriteLineValid => '1'),
+        (SpriteID => 42, X => 10, Y => 20, SpriteLine => 65535, SpriteLineValid => '0'),
+        (SpriteID => 0, X => 0, Y => 0, SpriteLine => 0, SpriteLineValid => '1'),
+        (SpriteID => 1023, X => 1023, Y => 1023, SpriteLine => 1, SpriteLineValid => '1')
+    );
+begin
+
+    ClockProc : process
+    begin
+        while TestDone = false loop
+            I_CLK <= '0';
+            wait for K_CLKPeriod / 2;
+            I_CLK <= '1';
+            wait for K_CLKPeriod / 2;
+        end loop;
+
+        I_CLK <= '0';
+        stop(0);
+        wait;
+    end process;
+
+    SpriteChannel_RegisterFile_inst : entity work.RegisterFile
+        generic map(
+            G_SpriteAddrWidth => G_SpriteIDWidth,
+            G_LineData_Width => G_SpriteLineWidth,
+            G_X_Width => G_XWidth,
+            G_Y_Width => G_YWidth
+        )
+        port map(
+            I_CLK => I_CLK,
+            I_CE => I_CE,
+            I_RST => I_RST,
+            I_SpriteAddr_WE => I_SpriteID_WE,
+            I_SpriteAddr => I_SpriteID,
+            I_X_We => I_X_WE,
+            I_X => I_X,
+            I_Y_WE => I_Y_WE,
+            I_Y => I_Y,
+            I_CachedLineData_WE => I_SpriteLine_WE,
+            I_CachedLineData => I_SpriteLine,
+            I_CacheValid_WE => I_SpriteLineValid_WE,
+            I_CacheValid => I_SpriteLineValid,
+            O_SpriteAddr => O_SpriteID,
+            O_X => O_X,
+            O_Y => O_Y,
+            O_CachedRowData => O_SpriteLine,
+            O_CacheValid => O_SpriteLineValid
+        );
+
+    StimulusProc : process
+        variable i : integer;
+    begin
+        -- Init
+        i := 0;
+        I_CE <= '1';
+        I_RST <= '1';
+        I_SpriteID_WE <= '0';
+        I_SpriteID <= (others => '0');
+        I_X_WE <= '0';
+        I_X <= (others => '0');
+        I_Y_WE <= '0';
+        I_Y <= (others => '0');
+        I_SpriteLine_WE <= '0';
+        I_SpriteLine <= (others => '0');
+        I_SpriteLineValid_WE <= '0';
+        I_SpriteLineValid <= '0';
+        wait for K_CLKPeriod * 2;
+        I_RST <= '0';
+        wait for K_CLKPeriod * 2;
+
+        for i in TestValues'range loop
+            -- WRITE phase
+            I_SpriteID <= std_logic_vector(to_unsigned(TestValues(i).SpriteID, G_SpriteIDWidth));
+            I_SpriteID_WE <= '1';
+            I_X <= std_logic_vector(to_unsigned(TestValues(i).X, G_XWidth));
+            I_X_WE <= '1';
+            I_Y <= std_logic_vector(to_unsigned(TestValues(i).Y, G_YWidth));
+            I_Y_WE <= '1';
+            I_SpriteLine <= std_logic_vector(to_unsigned(TestValues(i).SpriteLine, G_SpriteLineWidth));
+            I_SpriteLine_WE <= '1';
+            I_SpriteLineValid <= TestValues(i).SpriteLineValid;
+            I_SpriteLineValid_WE <= '1';
+
+            wait until rising_edge(I_CLK);
+            -- deactivate write signals
+            I_SpriteID_WE <= '0';
+            I_X_WE <= '0';
+            I_Y_WE <= '0';
+            I_SpriteLine_WE <= '0';
+            I_SpriteLineValid_WE <= '0';
+
+            wait for K_CLKPeriod;
+
+            -- READ and CHECK
+            assert O_SpriteID = std_logic_vector(to_unsigned(TestValues(i).SpriteID, G_SpriteIDWidth))
+            report "Fehler: SpriteID falsch bei Test " & integer'image(i)
+                severity error;
+
+            assert O_X = std_logic_vector(to_unsigned(TestValues(i).X, G_XWidth))
+            report "Fehler: X falsch bei Test " & integer'image(i)
+                severity error;
+
+            assert O_Y = std_logic_vector(to_unsigned(TestValues(i).Y, G_YWidth))
+            report "Fehler: Y falsch bei Test " & integer'image(i)
+                severity error;
+
+            assert O_SpriteLine = std_logic_vector(to_unsigned(TestValues(i).SpriteLine, G_SpriteLineWidth))
+            report "Fehler: SpriteLine falsch bei Test " & integer'image(i)
+                severity error;
+
+            assert O_SpriteLineValid = TestValues(i).SpriteLineValid
+            report "Fehler: SpriteLineValid falsch bei Test " & integer'image(i)
+                severity error;
+
+            report "Test " & integer'image(i) & " erfolgreich." severity note;
+            wait for K_CLKPeriod;
+        end loop;
+
+        report "Alle Tests abgeschlossen." severity note;
+        TestDone <= true;
+        wait;
+    end process;
+end;