Add .gitignore and project configuration files for SpriteChannel

.gitignore

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+.locale/
+build/

project.cfg

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+## Main settings.. ##
+
+# Project name
+# @remark The name of the project is used as default name for the top module and the ucf file
+PROJECT = SpriteChannel
+
+# Target device
+# @example xc3s1200e-4-fg320 | xc5vlx50t-1-ff1136
+TARGET_PART = xc3s1200e-4-fg320
+
+# Path to the Xilinx ISE installation
+XILINX = /opt/Xilinx/14.7/ISE_DS/ISE
+
+# Optional the name of the top module (default is the project name)
+TOPLEVEL = SpriteChannel
+
+# Optional the path/name of the ucf file (default is the project name)
+CONSTRAINTS = src/SpriteChannel.ucf
+
+# Optional a target to copy the bit file to (make copy)
+# COPY_TARGET_DIR = 
+
+## ## ## ## ## ## ## ##
+# ---------------------
+
+## Source files settings.. ##
+# The source files to be compiled
+# @example `VSOURCE += src/main.v` (add a single Verilog file per line)
+# @example `VHDSOURCE += src/main.vhd` (add a single VHDL file per line)
+VHDSOURCE += ../Asynchronous-FIFO-AXI-Handshake/libs/Pipeline-AXI-Handshake/src/PipelineRegister.vhd
+VHDSOURCE += ../Asynchronous-FIFO-AXI-Handshake/libs/Pipeline-AXI-Handshake/src/PipelineController.vhd
+VHDSOURCE += ../Asynchronous-FIFO-AXI-Handshake/libs/Pipeline-AXI-Handshake/src/PipelineStage.vhd
+VHDSOURCE += ../Asynchronous-FIFO-AXI-Handshake/libs/Pipeline-AXI-Handshake/src/PipelineFilter.vhd
+VHDSOURCE += libs/PriorityEncoders.vhd
+VHDSOURCE += libs/AXI-HS-Scheduler/build/AXI_Handshaking_Scheduler_2.vhdl
+VHDSOURCE += libs/AXI-HS-Scheduler/build/AXI_Handshaking_Scheduler_4.vhdl
+VHDSOURCE += libs/AXI-HS-Scheduler/build/AXI_Handshaking_Scheduler_8.vhdl
+VHDSOURCE += libs/AXI-HS-Scheduler/build/AXI_Handshaking_Scheduler_16.vhdl
+VHDSOURCE += libs/AXI-HS-Scheduler/build/AXI_Handshaking_Scheduler_32.vhdl
+VHDSOURCE += libs/AXI-HS-Scheduler/build/AXI_Handshaking_Scheduler_64.vhdl
+VHDSOURCE += libs/AXI-HS-MUX/AXI_HS_MUX.vhd
+VHDSOURCE += libs/OPCodes.vhd
+
+VHDSOURCE += src/VerticalSpritePipeline.vhd
+VHDSOURCE += src/RegisterFile.vhd
+VHDSOURCE += src/OPDecoder.vhd
+VHDSOURCE += src/Rom.vhd
+VHDSOURCE += src/RomPackage.vhd
+VHDSOURCE += src/HorizontalSpritePipeline.vhd
+VHDSOURCE += src/SpriteChannel.vhd
+
+
+## Test files settings.. ##
+# The testbench files to be compiled
+# @example `VTEST += tests/main_tb.v` (add a single Verilog testbench file per line)
+# @example `VHDTEST += tests/main_tb.vhd` (add a single VHDL testbench file per line)
+
+# VHDTEST += test/Scheduler_tb.vhd
+# VHDTEST += test/OPDecoder_tb.vhd
+# VHDTEST += test/YHitCheck_tb.vhd
+# VHDTEST += test/SpriteChannel_tb.vhd
+# VHDTEST += test/RegisterFile_tb.vhd
+
+## ## ## ## ## ## ## ##
+# ---------------------
+
+## ISE executable settings.. ##
+
+# General command line options to be passed to all ISE executables (default is `-intstyle xflow`)
+# COMMON_OPTS = 
+
+# Options for the XST synthesizer
+#### Synthese Options (XST) #####
+
+# Optimization goal: prioritize speed or area.
+# Values: Speed | Area
+XST_OPTS += -opt_mode Speed
+
+# Optimization level: more aggressive optimizations at level 2.
+# Values: 1 | 2
+XST_OPTS += -opt_level 2
+
+# Use the new XST parser (recommended for modern designs).
+# Values: yes | no
+XST_OPTS += -use_new_parser yes
+
+# Preserve design hierarchy or allow flattening for optimization.
+# Values: Yes | No | Soft
+XST_OPTS += -keep_hierarchy No
+
+# Determines how hierarchy is preserved in the netlist.
+# Values: As_Optimized | Rebuilt
+XST_OPTS += -netlist_hierarchy As_Optimized
+
+# Global optimization strategy for nets.
+# Values: AllClockNets | Offset_In_Before | Offset_Out_After | Inpad_To_Outpad | Max_Delay
+XST_OPTS += -glob_opt AllClockNets
+
+## Misc ##
+
+# Enable reading of IP cores.
+# Values: YES | NO
+XST_OPTS += -read_cores YES
+
+# Do not write timing constraints into synthesis report.
+# Values: YES | NO
+XST_OPTS += -write_timing_constraints NO
+
+# Analyze paths across different clock domains.
+# Values: YES | NO
+XST_OPTS += -cross_clock_analysis NO
+
+# Character used to separate hierarchy levels in instance names.
+# Default: /
+XST_OPTS += -hierarchy_separator /
+
+# Delimiters used for bus signals.
+# Values: <> | [] | () | {}
+XST_OPTS += -bus_delimiter <>
+
+# Maintain original case of identifiers.
+# Values: Maintain | Upper | Lower
+XST_OPTS += -case Maintain
+
+# Target maximum utilization ratio for slices.
+# Values: 1–100
+XST_OPTS += -slice_utilization_ratio 100
+
+# Target maximum utilization ratio for BRAMs.
+# Values: 1–100
+XST_OPTS += -bram_utilization_ratio 100
+
+# Use Verilog 2001 syntax features.
+# Values: YES | NO
+XST_OPTS += -verilog2001 YES
+
+#### HDL Options ####
+
+## FSM ##
+
+# Extract FSMs (Finite State Machines) from HDL code.
+# Values: YES | NO
+XST_OPTS += -fsm_extract YES
+
+# Encoding strategy for FSMs.
+# Values: Auto | Gray | One-Hot | Johnson | Compact | Sequential | Speed1 | User
+XST_OPTS += -fsm_encoding Auto
+
+# Add safe logic for undefined FSM states.
+# Values: Yes | No
+XST_OPTS += -safe_implementation No
+
+# Structure used to implement FSMs.
+# Values: LUT | BRAM
+XST_OPTS += -fsm_style LUT
+
+## RAM/ROM ##
+
+# Extract RAM inference from HDL.
+# Values: Yes | No
+XST_OPTS += -ram_extract Yes
+
+# Style used to implement RAM.
+# Values: Auto | Block | Distributed
+XST_OPTS += -ram_style Auto
+
+# Extract ROM inference from HDL.
+# Values: Yes | No
+XST_OPTS += -rom_extract Yes
+
+# Style used for implementing ROM.
+# Values: Auto | Distributed | Block
+XST_OPTS += -rom_style Auto
+
+# Enable or disable automatic BRAM packing.
+# Values: YES | NO
+XST_OPTS += -auto_bram_packing NO
+
+## MUX/Decoder/Shift Register ##
+
+# Extract multiplexers where possible.
+# Values: Yes | No | Force
+XST_OPTS += -mux_extract Yes
+
+# Style used for implementing MUX logic.
+# Values: Auto | MUXCY | MUXF
+XST_OPTS += -mux_style Auto
+
+# Extract decoder logic from behavioral code.
+# Values: YES | NO
+XST_OPTS += -decoder_extract YES
+
+# Extract and optimize priority encoder structures.
+# Values: Yes | No | Force
+XST_OPTS += -priority_extract Yes
+
+# Extract shift register logic.
+# Values: YES | NO
+XST_OPTS += -shreg_extract YES
+
+# Extract simple shift operations into dedicated hardware.
+# Values: YES | NO
+XST_OPTS += -shift_extract YES
+
+## Multiplier ##
+
+# Style for implementing multipliers.
+# Values: Auto | LUT | Pipe_LUT | Pipe_Block | Block
+XST_OPTS += -mult_style Auto
+
+## Misc ##
+
+# Collapse XOR trees where beneficial.
+# Values: YES | NO
+XST_OPTS += -xor_collapse YES
+
+# Share resources like adders or multipliers between logic blocks.
+# Values: YES | NO | Force
+XST_OPTS += -resource_sharing YES
+
+# Convert asynchronous resets to synchronous where possible.
+# Values: YES | NO
+XST_OPTS += -async_to_sync NO
+
+#### Xilinx Specific Options ####
+
+## Optimization ##
+
+# Enable removal of logically equivalent registers.
+# Values: YES | NO
+XST_OPTS += -equivalent_register_removal YES
+
+# Duplicate registers to reduce fanout or improve timing.
+# Values: YES | NO
+XST_OPTS += -register_duplication YES
+
+# Move registers across logic to balance timing.
+# Values: Yes | No | Forward | Backward
+XST_OPTS += -register_balancing No
+
+# Use clock enable signals where possible.
+# Values: Auto | Yes | No
+XST_OPTS += -use_clock_enable Yes
+
+# Use synchronous set (preset) signals when available.
+# Values: Auto | Yes | No
+XST_OPTS += -use_sync_set Yes
+
+# Use synchronous reset signals where possible.
+# Values: Auto | Yes | No
+XST_OPTS += -use_sync_reset Yes
+
+## I/O ##
+
+# Insert IO buffers for top-level ports.
+# Values: YES | NO
+XST_OPTS += -iobuf YES
+
+# Placement strategy for IOB registers (Auto = let tools decide).
+# Values: Auto | YES | NO
+XST_OPTS += -iob Auto
+
+## Misc ##
+
+# Maximum allowed fanout for a net.
+# Values: integer (e.g., 500)
+XST_OPTS += -max_fanout 500
+
+# Maximum number of BUFGs (global buffers) to use.
+# Values: 0–32 (device-dependent)
+XST_OPTS += -bufg 24
+
+# Enable logic packing into slices.
+# Values: YES | NO
+XST_OPTS += -slice_packing YES
+
+# Try to reduce the number of primitive instances used.
+# Values: YES | NO
+XST_OPTS += -optimize_primitives NO
+
+# Margin in percent beyond the target slice utilization.
+# Values: 0–100
+XST_OPTS += -slice_utilization_ratio_maxmargin 5
+
+
+# Options for the NGDBuild tool
+# NGDBUILD_OPTS =
+
+# Options for the MAP tool
+# @example -mt 2 (multi-threading with 2 threads)
+# @example -cm speed (speed optimization)
+# @example -ol high
+# @example -detail
+# @example -timing
+MAP_OPTS = -detail -timing -ol high
+
+# Options for the PAR tool
+# @example -mt 2 (multi-threading with 2 threads)
+# @example -ol high
+PAR_OPTS = -ol high
+
+# Options for the BitGen tool
+# @example -g Compress (compress bitstream)
+# @example -g StartupClk:Cclk (specify the startup clock to onboard clock)
+# @example -g StartupClk:JtagClk (specify the startup clock to JTAG clock)
+BITGEN_OPTS = -g StartupClk:JtagClk
+
+# Options for the Trace tool
+# TRACE_OPTS =
+
+# Options for the Fuse tool
+# FUSE_OPTS = 
+
+# Options for the ISim simulator
+# @example -gui (start the simulator in GUI mode)
+# ISIM_OPTS =
+
+# Options for the ISim batch file
+# @example vcd dumpfile $@.vcd \n vcd dumpvars -m /UUT \n run 1 sec \n vcd dumpflush \n quit
+# ISIM_CMD = vcd dumpfile $@.vcd \n vcd dumpvars -m /UUT \n run 1 sec \n vcd dumpflush \n quit
+
+## ## ## ## ## ## ## ##
+# ---------------------
+
+## Programmer settings.. ##
+
+# The programmer to use
+# @example impact | digilent | xc3sprog
+# @remark impact is the default Xilinx programmer and you must create a impact.cmd file in the root directory..
+PROGRAMMER = 
+
+## Digilent JTAG cable settings
+
+# @remark Use the `djtgcfg enum` command to list all available devices
+# DJTG_DEVICE = DOnbUsb
+
+# The index of the JTAG device for the `prog` target
+# DJTG_INDEX = 0
+
+# The index of the flash device for the `flash` target
+# DJTG_FLASH_INDEX = 1
+
+## ## ## ## ## ## ## ##
+# ---------------------