HDL/SpriteChannel
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Update build process and add Pipeline-AXI-Handshake sources

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0xMax42
2025-04-22 17:10:07 +00:00
parent df51a9ea92
commit 08fe7f8570
3 changed files with 9 additions and 5 deletions
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9
project.cfg
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@@ -27,10 +27,6 @@ CONSTRAINTS = src/SpriteChannel.ucf
# The source files to be compiled
# @example `VSOURCE += src/main.v` (add a single Verilog file per line)
# @example `VHDSOURCE += src/main.vhd` (add a single VHDL file per line)
VHDSOURCE += ../Asynchronous-FIFO-AXI-Handshake/libs/Pipeline-AXI-Handshake/src/PipelineRegister.vhd
VHDSOURCE += ../Asynchronous-FIFO-AXI-Handshake/libs/Pipeline-AXI-Handshake/src/PipelineController.vhd
VHDSOURCE += ../Asynchronous-FIFO-AXI-Handshake/libs/Pipeline-AXI-Handshake/src/PipelineStage.vhd
VHDSOURCE += ../Asynchronous-FIFO-AXI-Handshake/libs/Pipeline-AXI-Handshake/src/PipelineFilter.vhd
# VHDSOURCE += libs/PriorityEncoders.vhd
# VHDSOURCE += libs/AXI-HS-Scheduler/build/AXI_Handshaking_Scheduler_2.vhdl
# VHDSOURCE += libs/AXI-HS-Scheduler/build/AXI_Handshaking_Scheduler_4.vhdl
@@ -48,6 +44,11 @@ VHDSOURCE += src/Rom.vhd
VHDSOURCE += src/RomPackage.vhd
VHDSOURCE += src/HorizontalSpritePipeline.vhd
VHDSOURCE += src/SpriteChannel.vhd
VHDSOURCE += libs/Pipeline-AXI-Handshake/src/PipelineRegister.vhd
VHDSOURCE += libs/Pipeline-AXI-Handshake/src/PipelineController.vhd
VHDSOURCE += libs/Pipeline-AXI-Handshake/src/PipelineStage.vhd
VHDSOURCE += libs/Pipeline-AXI-Handshake/src/PipelineFilter.vhd
## Test files settings.. ##