MaxP
aae0a66fec
Introduces conditional logic to handle cases with zero pipeline stages, improving adaptability. Adds default values for generics and ports to enhance usability and reduce configuration errors. Cleans up formatting for better readability and maintainability. Relates to improved design modularity.
168 lines
7.4 KiB
VHDL
168 lines
7.4 KiB
VHDL
----------------------------------------------------------------------------------
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--@ - Name: **Pipeline Controller**
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--@ - Version: 0.0.2
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--@ - Author: _Maximilian Passarello ([Blog](mpassarello.de))_
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--@ - License: [MIT](LICENSE)
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--@
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--@ The Pipeline Controller provides an easy way to construct a pipeline
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--@ with AXI-Like handshaking at the input and output of the pipeline.
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--@
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--@ ### Core functions
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--@
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--@ - **Data flow control**: Data flow control is implemented via handshaking at the input and output ports.
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--@ - **Validity control**: The controller keeps the validity of the data in the individual pipeline stages under control.
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--@ - **Adjustability**: The pipeline controller can be customized via the generics.
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--@
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--@ ### Generics
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--@
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--@ Use the generic `G_PipelineStages` to set how deep the pipeline is.
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--@ This depth contains all the registers associated with the pipeline.
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--@ For example, for an _I_FF ⇨ Combinatorics ⇨ O_FF_ construction, the generic must be set to **2**.
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--@
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--@ The active level of the reset input can also be set.
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--@
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--@ ### Clock Enable
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--@
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--@ The `I_CE` port is active high and, when deactivated,
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--@ effectively switches on the acceptance or output of data via handshaking in addition to the pipeline.
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--@
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--@ ### Reset
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--@
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--@ A reset is explicitly **not** necessary on the pipeline registers.
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--@ The validity of the data is kept under control via the pipeline controller
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--@ and only this requires a dedicated reset if necessary.
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--@
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--@ ### Pipeline control
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--@
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--@ You must connect the `O_Enable` port to the CE input of the corresponding pipeline registers.
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--@ This is used to activate or deactivate the pipeline in full or via CE deactivated state.
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--@
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--@ ### AXI like Handshaking
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--@
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--@ - **Input**: The `O_Ready` (active high) port is used to signal to the data-supplying component that data should be accepted.
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--@ If it switches on `I_Valid` (active high), this in turn signals that data is ready to be accepted at its output.
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--@ If both ports are active at the same time, the transfer is executed.
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--@ - **Output**: The process runs analogously at the pipeline output.
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--@
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--@ ## History
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--@ - 0.0.1 (2024-03-24) Initial version
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--@ - 0.0.2 (2024-04-13) Enhanced the validity update logic to correctly handle configurations with a single pipeline stage
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----------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.math_real.all;
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entity PipelineController is
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generic (
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--@ Number of pipeline stages (FFs in the pipeline including I/O FFs)
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G_PipelineStages : integer := 3;
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--@ Reset active at this level
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G_ResetActiveAt : std_logic := '1'
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);
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port (
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--@ Clock signal; **Rising edge** triggered
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I_CLK : in std_logic := '0';
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--@ Reset signal; Active at `G_ResetActiveAt`
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I_RST : in std_logic := '0';
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--@ Chip enable; Active high
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I_CE : in std_logic := '1';
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--@ Pipeline enable; Active high when pipeline can accept data and `I_CE` is high. <br>
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--@ **Note:** Connect `CE` of the registers to be controlled by this controller to `O_Enable`.
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O_Enable : out std_logic := '0';
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--@ @virtualbus Input-AXI-Handshake @dir in Input AXI like Handshake
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--@ Valid data flag; indicates that the data on `I_Data` of the connected registers is valid.
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I_Valid : in std_logic := '0';
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--@ Ready flag; indicates that the connected registers is ready to accept data.
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O_Ready : out std_logic := '0';
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--@ @end
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--@ @virtualbus Output-AXI-Handshake @dir out Output AXI like Handshake
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--@ Valid data flag; indicates that the data on `O_Data` of the connected registers is valid.
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O_Valid : out std_logic := '0';
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--@ Ready flag; indicates that the external component is ready to accept data.
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I_Ready : in std_logic := '0'
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--@ @end
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);
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end entity PipelineController;
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architecture RTL of PipelineController is
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--@ Pipeline ready signal for each stage of the pipeline to indicate that the data in pipeline is valid
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signal R_Valid : std_logic_vector(G_PipelineStages - 1 downto 0) := (others => '0');
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--@ Ready signal for the pipeline controller to indicate that the pipeline can accept data; <br>
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--@ mapped to `O_Enable` and `O_Ready` ports.
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signal C_Ready : std_logic := '1';
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begin
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GEN_ForwardExternalFlags : if G_PipelineStages = 0 generate
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--@ If no pipeline stages are defined, the flags are directly connected to the input and output ports.
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P_ExternalFlags : process (I_CE, I_Valid, I_Ready)
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begin
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O_Valid <= I_Valid;
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O_Enable <= I_Ready and I_CE;
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O_Ready <= I_Ready and I_CE;
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end process;
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end generate;
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GEN_ExternalFlags : if G_PipelineStages > 0 generate
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--@ Produce the `O_Valid`, `O_Enable`, and `O_Ready` signals for the pipeline controller. <br>
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--@ - `O_Enable`, and `O_Ready` are **and** combined from the `C_Ready` and `I_CE` signals. <br>
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--@ - `O_Valid` is the last bit of the `R_Valid` signal
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--@ and represents the validity of the data in the last stage of the pipeline.
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P_ExternalFlags : process (R_Valid, C_Ready, I_CE)
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begin
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O_Valid <= R_Valid(R_Valid'high);
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O_Enable <= C_Ready and I_CE;
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O_Ready <= C_Ready and I_CE;
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end process;
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end generate;
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GEN_InternalFlags : if G_PipelineStages > 0 generate
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--@ Produce the `C_Ready` signal for the pipeline controller,
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--@ controlling the data flow in the pipeline. <br>
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--@ `C_Ready` is asserted when the data is available in the last stage of the pipeline
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--@ **and** the external component is ready to accept data
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--@ **or** when no data is available in the last stage of the pipeline.
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P_InternalFlags : process (R_Valid, I_Ready)
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begin
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if R_Valid(R_Valid'high) = '1' then
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-- Data is available in the last stage of the pipeline.
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if I_Ready = '1' then
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-- O_Data is accepted from the external component.
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C_Ready <= '1';
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else
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-- O_Data is not accepted from the external component.
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C_Ready <= '0';
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end if;
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else
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-- No data available in the last stage of the pipeline.
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C_Ready <= '1';
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end if;
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end process;
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end generate;
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GEN_ValidPipe : if G_PipelineStages > 0 generate
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--@ Shift the pipeline stages with `R_Valid` signal as placeholder to control
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--@ the validity of the data in the individual pipeline stages.
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P_ValidPipeline : process (I_CLK)
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begin
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if rising_edge(I_CLK) then
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if I_RST = G_ResetActiveAt then
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R_Valid <= (others => '0');
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elsif I_CE = '1' then
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if C_Ready = '1' then
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if G_PipelineStages = 1 then
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R_Valid(0) <= I_Valid;
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else
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R_Valid <= R_Valid(R_Valid'high - 1 downto R_Valid'low) & I_Valid;
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end if;
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end if;
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end if;
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end if;
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end process;
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end generate;
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end architecture RTL;
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