Adds devcontainer configuration and updates project structure to hdlbuild

.devcontainer/devcontainer.json

@@ -0,0 +1,25 @@
+{
+  "name": "Xilinx ISE 14.7",
+  "image": "xilinx-ise:14.7",
+  "runArgs": [
+    "--privileged",
+    "--cap-add=SYS_ADMIN",
+    "--shm-size=2g"
+  ],
+  "customizations": {
+    "vscode": {
+      "extensions": [
+        "/home/xilinx/vsxirepo/vhdl-by-hgb.vsix",
+        "eamodio.gitlens"
+      ],
+      "settings": {
+        "terminal.integrated.defaultProfile.linux": "bash"
+      }
+    }
+  },
+  "remoteUser": "xilinx",
+  "workspaceMount": "source=${localWorkspaceFolder},target=/workspaces/${localWorkspaceFolderBasename},type=bind",
+  "workspaceFolder": "/workspaces/${localWorkspaceFolderBasename}",
+  "features": {},
+  "forwardPorts": [10000]
+}

.gitmodules

@@ -1,3 +0,0 @@
-[submodule "build"]
-	path = build
-	url = https://github.com/PxaMMaxP/Xilinx-ISE-Makefile.git

project.cfg

@@ -1,308 +0,0 @@
-## Main settings.. ##
-
-# Project name
-# @remark The name of the project is used as default name for the top module and the ucf file
-PROJECT = Pipeline
-
-# Target device
-# @example xc3s1200e-4-fg320 | xc5vlx50t-1-ff1136
-TARGET_PART = xc3s1200e-4-fg320
-
-# Path to the Xilinx ISE installation
-XILINX = /opt/Xilinx/14.7/ISE_DS/ISE
-
-# Optional the name of the top module (default is the project name)
-TOPLEVEL = PipelineFilter
-
-# Optional the name of the ucf file (default is the project name)
-CONSTRAINTS = src/Pipeline_pb.ucf
-
-## ## ## ## ## ## ## ##
-# ---------------------
-
-## Source files settings.. ##
-# The source files to be compiled
-# @example `VSOURCE += src/main.v` (add a single Verilog file per line)
-# @example `VHDSOURCE += src/main.vhd` (add a single VHDL file per line)
-
-VHDSOURCE += src/Pipeline_pb.vhd
-VHDSOURCE += src/PipelineController.vhd
-VHDSOURCE += src/PipelineRegister.vhd
-VHDSOURCE += src/PipelineFilter.vhd
-VHDSOURCE += src/PipelineSwitch.vhd
-
-# VHDTEST += tests/Pipeline_tb.vhd
-# VHDTEST += tests/PipelineFilter_tb.vhd
-VHDTEST += tests/PipelineSwitch_tb.vhd
-
-## ## ## ## ## ## ## ##
-# ---------------------
-
-## ISE executable settings.. ##
-
-# General command line options to be passed to all ISE executables (default is `-intstyle xflow`)
-# COMMON_OPTS = 
-
-# Options for the XST synthesizer
-#### Synthese Options (XST) #####
-
-# Optimization goal: prioritize speed or area.
-# Values: Speed | Area
-XST_OPTS += -opt_mode Speed
-
-# Optimization level: more aggressive optimizations at level 2.
-# Values: 1 | 2
-XST_OPTS += -opt_level 2
-
-# Use the new XST parser (recommended for modern designs).
-# Values: yes | no
-XST_OPTS += -use_new_parser yes
-
-# Preserve design hierarchy or allow flattening for optimization.
-# Values: Yes | No | Soft
-XST_OPTS += -keep_hierarchy No
-
-# Determines how hierarchy is preserved in the netlist.
-# Values: As_Optimized | Rebuilt
-XST_OPTS += -netlist_hierarchy As_Optimized
-
-# Global optimization strategy for nets.
-# Values: AllClockNets | Offset_In_Before | Offset_Out_After | Inpad_To_Outpad | Max_Delay
-XST_OPTS += -glob_opt AllClockNets
-
-## Misc ##
-
-# Enable reading of IP cores.
-# Values: YES | NO
-XST_OPTS += -read_cores YES
-
-# Do not write timing constraints into synthesis report.
-# Values: YES | NO
-XST_OPTS += -write_timing_constraints NO
-
-# Analyze paths across different clock domains.
-# Values: YES | NO
-XST_OPTS += -cross_clock_analysis NO
-
-# Character used to separate hierarchy levels in instance names.
-# Default: /
-XST_OPTS += -hierarchy_separator /
-
-# Delimiters used for bus signals.
-# Values: <> | [] | () | {}
-XST_OPTS += -bus_delimiter <>
-
-# Maintain original case of identifiers.
-# Values: Maintain | Upper | Lower
-XST_OPTS += -case Maintain
-
-# Target maximum utilization ratio for slices.
-# Values: 1–100
-XST_OPTS += -slice_utilization_ratio 100
-
-# Target maximum utilization ratio for BRAMs.
-# Values: 1–100
-XST_OPTS += -bram_utilization_ratio 100
-
-# Use Verilog 2001 syntax features.
-# Values: YES | NO
-XST_OPTS += -verilog2001 YES
-
-#### HDL Options ####
-
-## FSM ##
-
-# Extract FSMs (Finite State Machines) from HDL code.
-# Values: YES | NO
-XST_OPTS += -fsm_extract YES
-
-# Encoding strategy for FSMs.
-# Values: Auto | Gray | One-Hot | Johnson | Compact | Sequential | Speed1 | User
-XST_OPTS += -fsm_encoding Auto
-
-# Add safe logic for undefined FSM states.
-# Values: Yes | No
-XST_OPTS += -safe_implementation No
-
-# Structure used to implement FSMs.
-# Values: LUT | BRAM
-XST_OPTS += -fsm_style LUT
-
-## RAM/ROM ##
-
-# Extract RAM inference from HDL.
-# Values: Yes | No
-XST_OPTS += -ram_extract Yes
-
-# Style used to implement RAM.
-# Values: Auto | Block | Distributed
-XST_OPTS += -ram_style Auto
-
-# Extract ROM inference from HDL.
-# Values: Yes | No
-XST_OPTS += -rom_extract Yes
-
-# Style used for implementing ROM.
-# Values: Auto | Distributed | Block
-XST_OPTS += -rom_style Auto
-
-# Enable or disable automatic BRAM packing.
-# Values: YES | NO
-XST_OPTS += -auto_bram_packing NO
-
-## MUX/Decoder/Shift Register ##
-
-# Extract multiplexers where possible.
-# Values: Yes | No | Force
-XST_OPTS += -mux_extract Yes
-
-# Style used for implementing MUX logic.
-# Values: Auto | MUXCY | MUXF
-XST_OPTS += -mux_style Auto
-
-# Extract decoder logic from behavioral code.
-# Values: YES | NO
-XST_OPTS += -decoder_extract YES
-
-# Extract and optimize priority encoder structures.
-# Values: Yes | No | Force
-XST_OPTS += -priority_extract Yes
-
-# Extract shift register logic.
-# Values: YES | NO
-XST_OPTS += -shreg_extract YES
-
-# Extract simple shift operations into dedicated hardware.
-# Values: YES | NO
-XST_OPTS += -shift_extract YES
-
-## Multiplier ##
-
-# Style for implementing multipliers.
-# Values: Auto | LUT | Pipe_LUT | Pipe_Block | Block
-XST_OPTS += -mult_style Auto
-
-## Misc ##
-
-# Collapse XOR trees where beneficial.
-# Values: YES | NO
-XST_OPTS += -xor_collapse YES
-
-# Share resources like adders or multipliers between logic blocks.
-# Values: YES | NO | Force
-XST_OPTS += -resource_sharing YES
-
-# Convert asynchronous resets to synchronous where possible.
-# Values: YES | NO
-XST_OPTS += -async_to_sync NO
-
-#### Xilinx Specific Options ####
-
-## Optimization ##
-
-# Enable removal of logically equivalent registers.
-# Values: YES | NO
-XST_OPTS += -equivalent_register_removal YES
-
-# Duplicate registers to reduce fanout or improve timing.
-# Values: YES | NO
-XST_OPTS += -register_duplication YES
-
-# Move registers across logic to balance timing.
-# Values: Yes | No
-XST_OPTS += -register_balancing No
-
-# Use clock enable signals where possible.
-# Values: Auto | Yes | No
-XST_OPTS += -use_clock_enable Yes
-
-# Use synchronous set (preset) signals when available.
-# Values: Auto | Yes | No
-XST_OPTS += -use_sync_set Yes
-
-# Use synchronous reset signals where possible.
-# Values: Auto | Yes | No
-XST_OPTS += -use_sync_reset Yes
-
-## I/O ##
-
-# Insert IO buffers for top-level ports.
-# Values: YES | NO
-XST_OPTS += -iobuf YES
-
-# Placement strategy for IOB registers (Auto = let tools decide).
-# Values: Auto | YES | NO
-XST_OPTS += -iob Auto
-
-## Misc ##
-
-# Maximum allowed fanout for a net.
-# Values: integer (e.g., 500)
-XST_OPTS += -max_fanout 500
-
-# Maximum number of BUFGs (global buffers) to use.
-# Values: 0–32 (device-dependent)
-XST_OPTS += -bufg 24
-
-# Enable logic packing into slices.
-# Values: YES | NO
-XST_OPTS += -slice_packing YES
-
-# Try to reduce the number of primitive instances used.
-# Values: YES | NO
-XST_OPTS += -optimize_primitives NO
-
-# Margin in percent beyond the target slice utilization.
-# Values: 0–100
-XST_OPTS += -slice_utilization_ratio_maxmargin 5
-
-
-
-# Options for the NGDBuild tool
-# NGDBUILD_OPTS =
-
-# Options for the MAP tool
-# @example -mt 2 (multi-threading with 2 threads)
-MAP_OPTS = -cm speed -ol high -detail -timing
-
-# Options for the PAR tool
-# @example -mt 2 (multi-threading with 2 threads)
-PAR_OPTS = -ol high
-
-# Options for the BitGen tool
-# @example -g Compress (compress bitstream)
-# @example -g StartupClk:Cclk (specify the startup clock to onboard clock)
-# @example -g StartupClk:JtagClk (specify the startup clock to JTAG clock)
-# BITGEN_OPTS = 
-
-# Options for the Trace tool
-# TRACE_OPTS = 
-
-# Options for the Fuse tool
-# FUSE_OPTS = 
-
-# ISIM_CMD = 
-
-## ## ## ## ## ## ## ##
-# ---------------------
-
-## Programmer settings.. ##
-
-# The programmer to use
-# @example impact | digilent | xc3sprog
-# @remark impact is the default Xilinx programmer and you must create a impact.cmd file in the root directory..
-PROGRAMMER = 
-
-## Digilent JTAG cable settings
-
-# @remark Use the `djtgcfg enum` command to list all available devices
-# DJTG_DEVICE = DOnbUsb
-
-# The index of the JTAG device for the `prog` target
-# DJTG_INDEX = 0
-
-# The index of the flash device for the `flash` target
-# DJTG_FLASH_INDEX = 1
-
-## ## ## ## ## ## ## ##
-# ---------------------

project.yml

@@ -0,0 +1,265 @@
+name: Pipeline-AXI-Handshake
+topmodule: Pipeline_pb
+target_device: xc3s1200e-4-fg320
+xilinx_path: /opt/Xilinx/14.7/ISE_DS/ISE
+
+sources:
+  vhdl:
+    - path: src/*.vhd
+      library: work
+
+constraints: src/Pipeline_pb.ucf
+
+testbenches:
+  vhdl:
+    - path: tests/*.vhd
+      library: work
+
+dependencies: []
+
+build:
+  build_dir: working
+  report_dir: reports
+  copy_target_dir: output
+
+# Tool Optionen
+tool_options:
+  common: 
+    - "-intstyle"
+    - "xflow"
+
+  ngdbuild: []
+
+  map: 
+    - "-detail"
+    - "-timing"
+    - "-ol high"
+
+  par: []
+
+  bitgen: 
+    - "-g"
+    - "StartupClk:JtagClk"
+
+  trace:
+    - "-v"
+    - "3"
+    - "-n"
+    - "3"
+
+  fuse: 
+    - "-incremental"
+
+  isim: 
+    - "-gui"
+
+  xst: 
+    # Optimization goal: prioritize speed or area.
+    # Values: Speed | Area
+    - "-opt_mode Speed"
+
+    # Optimization level: more aggressive optimizations at level 2.
+    # Values: 1 | 2
+    - "-opt_level 2"
+
+    # Use the new XST parser (recommended for modern designs).
+    # Values: yes | no
+    - "-use_new_parser yes"
+
+    # Preserve design hierarchy or allow flattening for optimization.
+    # Values: Yes | No | Soft
+    - "-keep_hierarchy No"
+
+    # Determines how hierarchy is preserved in the netlist.
+    # Values: As_Optimized | Rebuilt
+    - "-netlist_hierarchy As_Optimized"
+
+    # Global optimization strategy for nets.
+    # Values: AllClockNets | Offset_In_Before | Offset_Out_After | Inpad_To_Outpad | Max_Delay
+    - "-glob_opt AllClockNets"
+
+    ## Misc ##
+
+    # Enable reading of IP cores.
+    # Values: YES | NO
+    - "-read_cores YES"
+
+    # Do not write timing constraints into synthesis report.
+    # Values: YES | NO
+    - "-write_timing_constraints NO"
+
+    # Analyze paths across different clock domains.
+    # Values: YES | NO
+    - "-cross_clock_analysis NO"
+
+    # Character used to separate hierarchy levels in instance names.
+    # Default: /
+    - "-hierarchy_separator /"
+
+    # Delimiters used for bus signals.
+    # Values: <> | [] | () | {}
+    - "-bus_delimiter <>"
+
+    # Maintain original case of identifiers.
+    # Values: Maintain | Upper | Lower
+    - "-case Maintain"
+
+    # Target maximum utilization ratio for slices.
+    # Values: 1–100
+    - "-slice_utilization_ratio 100"
+
+    # Target maximum utilization ratio for BRAMs.
+    # Values: 1–100
+    - "-bram_utilization_ratio 100"
+
+    # Use Verilog 2001 syntax features.
+    # Values: YES | NO
+    - "-verilog2001 YES"
+
+    #### HDL Options ####
+
+    ## FSM ##
+
+    # Extract FSMs (Finite State Machines) from HDL code.
+    # Values: YES | NO
+    - "-fsm_extract YES"
+
+    # Encoding strategy for FSMs.
+    # Values: Auto | Gray | One-Hot | Johnson | Compact | Sequential | Speed1 | User
+    - "-fsm_encoding Auto"
+
+    # Add safe logic for undefined FSM states.
+    # Values: Yes | No
+    - "-safe_implementation No"
+
+    # Structure used to implement FSMs.
+    # Values: LUT | BRAM
+    - "-fsm_style LUT"
+
+    ## RAM/ROM ##
+
+    # Extract RAM inference from HDL.
+    # Values: Yes | No
+    - "-ram_extract Yes"
+
+    # Style used to implement RAM.
+    # Values: Auto | Block | Distributed
+    - "-ram_style Auto"
+
+    # Extract ROM inference from HDL.
+    # Values: Yes | No
+    - "-rom_extract Yes"
+
+    # Style used for implementing ROM.
+    # Values: Auto | Distributed | Block
+    - "-rom_style Auto"
+
+    # Enable or disable automatic BRAM packing.
+    # Values: YES | NO
+    - "-auto_bram_packing NO"
+
+    ## MUX/Decoder/Shift Register ##
+
+    # Extract multiplexers where possible.
+    # Values: Yes | No | Force
+    - "-mux_extract Yes"
+
+    # Style used for implementing MUX logic.
+    # Values: Auto | MUXCY | MUXF
+    - "-mux_style Auto"
+
+    # Extract decoder logic from behavioral code.
+    # Values: YES | NO
+    - "-decoder_extract YES"
+
+    # Extract and optimize priority encoder structures.
+    # Values: Yes | No | Force
+    - "-priority_extract Yes"
+
+    # Extract shift register logic.
+    # Values: YES | NO
+    - "-shreg_extract YES"
+
+    # Extract simple shift operations into dedicated hardware.
+    # Values: YES | NO
+    - "-shift_extract YES"
+
+    ## Multiplier ##
+
+    # Style for implementing multipliers.
+    # Values: Auto | LUT | Pipe_LUT | Pipe_Block | Block
+    - "-mult_style Auto"
+
+    ## Misc ##
+
+    # Collapse XOR trees where beneficial.
+    # Values: YES | NO
+    - "-xor_collapse YES"
+
+    # Share resources like adders or multipliers between logic blocks.
+    # Values: YES | NO | Force
+    - "-resource_sharing YES"
+
+    # Convert asynchronous resets to synchronous where possible.
+    # Values: YES | NO
+    - "-async_to_sync NO"
+
+    #### Xilinx Specific Options ####
+
+    ## Optimization ##
+
+    # Enable removal of logically equivalent registers.
+    # Values: YES | NO
+    - "-equivalent_register_removal YES"
+
+    # Duplicate registers to reduce fanout or improve timing.
+    # Values: YES | NO
+    - "-register_duplication YES"
+
+    # Move registers across logic to balance timing.
+    # Values: Yes | No | Forward | Backward
+    - "-register_balancing No"
+
+    # Use clock enable signals where possible.
+    # Values: Auto | Yes | No
+    - "-use_clock_enable Yes"
+
+    # Use synchronous set (preset) signals when available.
+    # Values: Auto | Yes | No
+    - "-use_sync_set Yes"
+
+    # Use synchronous reset signals where possible.
+    # Values: Auto | Yes | No
+    - "-use_sync_reset Yes"
+
+    ## I/O ##
+
+    # Insert IO buffers for top-level ports.
+    # Values: YES | NO
+    - "-iobuf YES"
+
+    # Placement strategy for IOB registers (Auto = let tools decide).
+    # Values: Auto | YES | NO
+    - "-iob Auto"
+
+    ## Misc ##
+
+    # Maximum allowed fanout for a net.
+    # Values: integer (e.g., 500)
+    - "-max_fanout 500"
+
+    # Maximum number of BUFGs (global buffers) to use.
+    # Values: 0–32 (device-dependent)
+    - "-bufg 24"
+
+    # Enable logic packing into slices.
+    # Values: YES | NO
+    - "-slice_packing YES"
+
+    # Try to reduce the number of primitive instances used.
+    # Values: YES | NO
+    - "-optimize_primitives NO"
+
+    # Margin in percent beyond the target slice utilization.
+    # Values: 0–100
+    - "-slice_utilization_ratio_maxmargin 5"

src/Pipeline_pb.vhd

@@ -21,7 +21,7 @@ entity Pipeline_pb is
         --@ - "forward": Moves a set of FFs at the inputs of a LUT to a single FF at its output. <br>
         --@ - "backward": Moves a single FF at the output of a LUT to a set of FFs at its inputs.
         G_RegisterBalancing : string  := "yes"
-    );
+        );
     port (
         I_CLK   : in  std_logic;
         I_RST   : in  std_logic;
@@ -32,29 +32,29 @@ entity Pipeline_pb is
         O_Data  : out std_logic_vector(G_Width - 1 downto 0);
         O_Valid : out std_logic;
         I_Ready : in  std_logic
-    );
+        );
 end entity Pipeline_pb;
 
 architecture RTL of Pipeline_pb is
     -- Keep attribute: Prevents the synthesis tool from removing the entity if is "true".
-    attribute keep                                     : string;
+    attribute keep : string;
     -- IOB attribute: Attaches the FF to the IOB if is "true".
-    attribute IOB                                      : string;
+    attribute IOB  : string;
 
     -- General Interace
-    signal R_RST                                       : std_logic;
+    signal R_RST                  : std_logic;
-    signal R_CE                                        : std_logic;
+    signal R_CE                   : std_logic;
     -- Attribute
-    attribute keep of R_RST, R_CE                      : signal is "true";
+    attribute keep of R_RST, R_CE : signal is "true";
-    attribute IOB of R_RST, R_CE                       : signal is "false";
+    attribute IOB of R_RST, R_CE  : signal is "false";
 
     -- Input Interface
-    signal R_DataIn                                    : std_logic_vector(G_Width - 1 downto 0);
+    signal R_DataIn                                   : std_logic_vector(G_Width - 1 downto 0);
-    signal R_ValidIn                                   : std_logic;
+    signal R_ValidIn                                  : std_logic;
-    signal R_ReadyOut                                  : std_logic;
+    signal R_ReadyOut                                 : std_logic;
     -- Attribute
-    attribute keep of R_DataIn, R_ValidIn, R_ReadyOut  : signal is "true";
+    attribute keep of R_DataIn, R_ValidIn, R_ReadyOut : signal is "true";
-    attribute IOB of R_DataIn, R_ValidIn, R_ReadyOut   : signal is "false";
+    attribute IOB of R_DataIn, R_ValidIn, R_ReadyOut  : signal is "false";
 
     -- Output Interface
     signal R_DataOut                                   : std_logic_vector(G_Width - 1 downto 0);
@@ -64,20 +64,20 @@ architecture RTL of Pipeline_pb is
     attribute keep of R_DataOut, R_ValidOut, R_ReadyIn : signal is "true";
     attribute IOB of R_DataOut, R_ValidOut, R_ReadyIn  : signal is "false";
 
-    signal C_Pipeline0Enable                           : std_logic;
+    signal C_Pipeline0Enable : std_logic;
-    signal C_Pipeline1Enable                           : std_logic;
+    signal C_Pipeline1Enable : std_logic;
 
-    signal R_Valid                                     : std_logic;
+    signal R_Valid : std_logic;
-    signal R_Ready                                     : std_logic;
+    signal R_Ready : std_logic;
-    signal R_Data                                      : std_logic_vector(G_Width - 1 downto 0);
+    signal R_Data  : std_logic_vector(G_Width - 1 downto 0);
 begin
 
     BenchmarkEnvironmentFFs : process (I_CLK)
     begin
         if rising_edge(I_CLK) then
             -- General Interace
-            R_RST     <= I_RST;
+            R_RST <= I_RST;
-            R_CE      <= I_CE;
+            R_CE  <= I_CE;
 
             -- Input Interface
             R_DataIn  <= I_Data;
@@ -95,7 +95,7 @@ begin
         generic map(
             G_PipelineStages => G_PipelineStages,
             G_ResetActiveAt  => '1'
-        )
+            )
         port map(
             I_CLK    => I_CLK,
             I_RST    => R_RST,
@@ -105,20 +105,20 @@ begin
             O_Ready  => R_ReadyOut,
             O_Valid  => R_Valid,
             I_Ready  => R_Ready
-        );
+            );
 
     PipelineRegisterIn : entity work.PipelineRegister
         generic map(
             G_PipelineStages    => G_PipelineStages,
             G_Width             => G_Width,
             G_RegisterBalancing => G_RegisterBalancing
-        )
+            )
         port map(
             I_CLK    => I_CLK,
             I_Enable => C_Pipeline0Enable,
             I_Data   => R_DataIn,
             O_Data   => R_Data
-        );
+            );
 
     ---------
 
@@ -126,7 +126,7 @@ begin
         generic map(
             G_PipelineStages => G_PipelineStages,
             G_ResetActiveAt  => '1'
-        )
+            )
         port map(
             I_CLK    => I_CLK,
             I_RST    => R_RST,
@@ -136,19 +136,19 @@ begin
             O_Ready  => R_Ready,
             O_Valid  => R_ValidOut,
             I_Ready  => R_ReadyIn
-        );
+            );
 
     PipelineRegisterOut : entity work.PipelineRegister
         generic map(
             G_PipelineStages    => G_PipelineStages,
             G_Width             => G_Width,
             G_RegisterBalancing => G_RegisterBalancing
-        )
+            )
         port map(
             I_CLK    => I_CLK,
             I_Enable => C_Pipeline1Enable,
             I_Data   => R_Data,
             O_Data   => R_DataOut
-        );
+            );
 
 end architecture RTL;