HDL/Pipeline-AXI-Handshake
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Adds devcontainer configuration and updates project structure to hdlbuild

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0xMax42
2025-04-27 17:46:05 +00:00
parent 454172e91c
commit c74b34f610
7 changed files with 318 additions and 340 deletions
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56
src/Pipeline_pb.vhd
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@@ -21,7 +21,7 @@ entity Pipeline_pb is
--@ - "forward": Moves a set of FFs at the inputs of a LUT to a single FF at its output. <br>
--@ - "backward": Moves a single FF at the output of a LUT to a set of FFs at its inputs.
G_RegisterBalancing : string := "yes"
);
);
port (
I_CLK : in std_logic;
I_RST : in std_logic;
@@ -32,29 +32,29 @@ entity Pipeline_pb is
O_Data : out std_logic_vector(G_Width - 1 downto 0);
O_Valid : out std_logic;
I_Ready : in std_logic
);
);
end entity Pipeline_pb;
architecture RTL of Pipeline_pb is
-- Keep attribute: Prevents the synthesis tool from removing the entity if is "true".
attribute keep : string;
attribute keep : string;
-- IOB attribute: Attaches the FF to the IOB if is "true".
attribute IOB : string;
attribute IOB : string;
-- General Interace
signal R_RST : std_logic;
signal R_CE : std_logic;
signal R_RST : std_logic;
signal R_CE : std_logic;
-- Attribute
attribute keep of R_RST, R_CE : signal is "true";
attribute IOB of R_RST, R_CE : signal is "false";
attribute keep of R_RST, R_CE : signal is "true";
attribute IOB of R_RST, R_CE : signal is "false";
-- Input Interface
signal R_DataIn : std_logic_vector(G_Width - 1 downto 0);
signal R_ValidIn : std_logic;
signal R_ReadyOut : std_logic;
signal R_DataIn : std_logic_vector(G_Width - 1 downto 0);
signal R_ValidIn : std_logic;
signal R_ReadyOut : std_logic;
-- Attribute
attribute keep of R_DataIn, R_ValidIn, R_ReadyOut : signal is "true";
attribute IOB of R_DataIn, R_ValidIn, R_ReadyOut : signal is "false";
attribute keep of R_DataIn, R_ValidIn, R_ReadyOut : signal is "true";
attribute IOB of R_DataIn, R_ValidIn, R_ReadyOut : signal is "false";
-- Output Interface
signal R_DataOut : std_logic_vector(G_Width - 1 downto 0);
@@ -64,20 +64,20 @@ architecture RTL of Pipeline_pb is
attribute keep of R_DataOut, R_ValidOut, R_ReadyIn : signal is "true";
attribute IOB of R_DataOut, R_ValidOut, R_ReadyIn : signal is "false";
signal C_Pipeline0Enable : std_logic;
signal C_Pipeline1Enable : std_logic;
signal C_Pipeline0Enable : std_logic;
signal C_Pipeline1Enable : std_logic;
signal R_Valid : std_logic;
signal R_Ready : std_logic;
signal R_Data : std_logic_vector(G_Width - 1 downto 0);
signal R_Valid : std_logic;
signal R_Ready : std_logic;
signal R_Data : std_logic_vector(G_Width - 1 downto 0);
begin
BenchmarkEnvironmentFFs : process (I_CLK)
begin
if rising_edge(I_CLK) then
-- General Interace
R_RST <= I_RST;
R_CE <= I_CE;
R_RST <= I_RST;
R_CE <= I_CE;
-- Input Interface
R_DataIn <= I_Data;
@@ -95,7 +95,7 @@ begin
generic map(
G_PipelineStages => G_PipelineStages,
G_ResetActiveAt => '1'
)
)
port map(
I_CLK => I_CLK,
I_RST => R_RST,
@@ -105,20 +105,20 @@ begin
O_Ready => R_ReadyOut,
O_Valid => R_Valid,
I_Ready => R_Ready
);
);
PipelineRegisterIn : entity work.PipelineRegister
generic map(
G_PipelineStages => G_PipelineStages,
G_Width => G_Width,
G_RegisterBalancing => G_RegisterBalancing
)
)
port map(
I_CLK => I_CLK,
I_Enable => C_Pipeline0Enable,
I_Data => R_DataIn,
O_Data => R_Data
);
);
---------
@@ -126,7 +126,7 @@ begin
generic map(
G_PipelineStages => G_PipelineStages,
G_ResetActiveAt => '1'
)
)
port map(
I_CLK => I_CLK,
I_RST => R_RST,
@@ -136,19 +136,19 @@ begin
O_Ready => R_Ready,
O_Valid => R_ValidOut,
I_Ready => R_ReadyIn
);
);
PipelineRegisterOut : entity work.PipelineRegister
generic map(
G_PipelineStages => G_PipelineStages,
G_Width => G_Width,
G_RegisterBalancing => G_RegisterBalancing
)
)
port map(
I_CLK => I_CLK,
I_Enable => C_Pipeline1Enable,
I_Data => R_Data,
O_Data => R_DataOut
);
);
end architecture RTL;