HDL/Pipeline-AXI-Handshake
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Refactors pipeline controllers and registers for flexibility

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Introduces conditional logic to handle cases with zero pipeline stages, improving adaptability.
Adds default values for generics and ports to enhance usability and reduce configuration errors.
Cleans up formatting for better readability and maintainability.

Relates to improved design modularity.
This commit is contained in:
0xMax42
2025-04-16 17:24:51 +00:00
parent 59e8302a48
commit aae0a66fec
3 changed files with 126 additions and 91 deletions
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2
.gitignore vendored
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@@ -1 +1,3 @@
build/working
.locale/
vhdl_ls.toml

36
src/PipelineController.vhd
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@@ -48,7 +48,6 @@
--@ - 0.0.1 (2024-03-24) Initial version
--@ - 0.0.2 (2024-04-13) Enhanced the validity update logic to correctly handle configurations with a single pipeline stage
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
@@ -63,25 +62,28 @@ entity PipelineController is
);
port (
--@ Clock signal; **Rising edge** triggered
I_CLK : in std_logic;
I_CLK : in std_logic := '0';
--@ Reset signal; Active at `G_ResetActiveAt`
I_RST : in std_logic;
I_RST : in std_logic := '0';
--@ Chip enable; Active high
I_CE : in std_logic;
I_CE : in std_logic := '1';
--@ Pipeline enable; Active high when pipeline can accept data and `I_CE` is high. <br>
--@ **Note:** Connect `CE` of the registers to be controlled by this controller to `O_Enable`.
O_Enable : out std_logic;
O_Enable : out std_logic := '0';
--@ @virtualbus Input-AXI-Handshake @dir in Input AXI like Handshake
--@ Valid data flag; indicates that the data on `I_Data` of the connected registers is valid.
I_Valid : in std_logic;
I_Valid : in std_logic := '0';
--@ Ready flag; indicates that the connected registers is ready to accept data.
O_Ready : out std_logic;
O_Ready : out std_logic := '0';
--@ @end
--@ @virtualbus Output-AXI-Handshake @dir out Output AXI like Handshake
--@ Valid data flag; indicates that the data on `O_Data` of the connected registers is valid.
O_Valid : out std_logic;
O_Valid : out std_logic := '0';
--@ Ready flag; indicates that the external component is ready to accept data.
I_Ready : in std_logic
I_Ready : in std_logic := '0'
--@ @end
);
end entity PipelineController;
@@ -94,6 +96,17 @@ architecture RTL of PipelineController is
signal C_Ready : std_logic := '1';
begin
GEN_ForwardExternalFlags : if G_PipelineStages = 0 generate
--@ If no pipeline stages are defined, the flags are directly connected to the input and output ports.
P_ExternalFlags : process (I_CE, I_Valid, I_Ready)
begin
O_Valid <= I_Valid;
O_Enable <= I_Ready and I_CE;
O_Ready <= I_Ready and I_CE;
end process;
end generate;
GEN_ExternalFlags : if G_PipelineStages > 0 generate
--@ Produce the `O_Valid`, `O_Enable`, and `O_Ready` signals for the pipeline controller. <br>
--@ - `O_Enable`, and `O_Ready` are **and** combined from the `C_Ready` and `I_CE` signals. <br>
--@ - `O_Valid` is the last bit of the `R_Valid` signal
@@ -105,7 +118,9 @@ begin
O_Enable <= C_Ready and I_CE;
O_Ready <= C_Ready and I_CE;
end process;
end generate;
GEN_InternalFlags : if G_PipelineStages > 0 generate
--@ Produce the `C_Ready` signal for the pipeline controller,
--@ controlling the data flow in the pipeline. <br>
--@ `C_Ready` is asserted when the data is available in the last stage of the pipeline
@@ -127,7 +142,9 @@ begin
C_Ready <= '1';
end if;
end process;
end generate;
GEN_ValidPipe : if G_PipelineStages > 0 generate
--@ Shift the pipeline stages with `R_Valid` signal as placeholder to control
--@ the validity of the data in the individual pipeline stages.
P_ValidPipeline : process (I_CLK)
@@ -146,4 +163,5 @@ begin
end if;
end if;
end process;
end generate;
end architecture RTL;

23
src/PipelineRegister.vhd
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@@ -52,12 +52,12 @@ entity PipelineRegister is
G_RegisterBalancing : string := "yes"
);
port (
--@ Clock signal; **Rising edge** triggered
I_CLK : in std_logic;
--@ Clock; (**Rising edge** triggered)
I_CLK : in std_logic := '0';
--@ Enable input from **Pipeline Controller**
I_Enable : in std_logic;
I_Enable : in std_logic := '0';
--@ Data input
I_Data : in std_logic_vector(G_Width - 1 downto 0);
I_Data : in std_logic_vector(G_Width - 1 downto 0) := (others => '0');
--@ Data output
O_Data : out std_logic_vector(G_Width - 1 downto 0) := (others => '0')
);
@@ -74,6 +74,8 @@ architecture RTL of PipelineRegister is
attribute register_balancing of R_Data : signal is G_RegisterBalancing;
begin
--@ Generate the pipeline registers if `G_PipelineStages` is greater than 0.
GEN_PipelineRegister : if G_PipelineStages > 0 generate
--@ Pipeline register and connection of the data from the input port to the first stage of the pipeline register. <br>
--@ **I_Data -> R_Data(0) -> R_Data(1) -> ... -> R_Data(G_PipelineStages - 1)** -> O_Data
P_PipelineRegister : process (I_CLK)
@@ -92,12 +94,25 @@ begin
end if;
end if;
end process;
end generate;
--@ Generate the connection last register to the output port if `G_PipelineStages` is greater than 0.
GEN_ForwardRegister : if G_PipelineStages > 0 generate
--@ Connect (combinatoric) data from the last stage of the pipeline register to the output port. <br>
--@ I_Data -> R_Data(0) -> R_Data(1) -> ... -> **R_Data(G_PipelineStages - 1) -> O_Data**
P_ForwardData : process (R_Data)
begin
O_Data <= R_Data(G_PipelineStages - 1);
end process;
end generate;
--@ Generate the connection of the input port to the output port if `G_PipelineStages` is 0.
GEN_ForwardData : if G_PipelineStages = 0 generate
--@ If `G_PipelineStages` is 0, the data from the input port is directly connected to the output port.
P_ForwardData : process (I_Data)
begin
O_Data <= I_Data;
end process;
end generate;
end architecture RTL;