HDL/Pipeline-AXI-Handshake
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Refactors pipeline controllers and registers for flexibility

Browse Source 
Introduces conditional logic to handle cases with zero pipeline stages, improving adaptability.
Adds default values for generics and ports to enhance usability and reduce configuration errors.
Cleans up formatting for better readability and maintainability.

Relates to improved design modularity.
This commit is contained in:
0xMax42
2025-04-16 17:24:51 +00:00
parent 59e8302a48
commit aae0a66fec
3 changed files with 126 additions and 91 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
.gitignore vendored
View File

@@ -1 +1,3 @@
build/working
build/working
.locale/
vhdl_ls.toml