feat: implements pipelined module chaining for performance
- Introduces a pipelined module and top-level wrapper for performance benchmarking. - Chains multiple pipeline modules in series to increase throughput. - Adds generics to control pipeline depth, data width, and register balancing. - Includes optional CE/RST enables and pipeline buffer.
This commit is contained in:
@@ -11,24 +11,36 @@ use ieee.math_real.all;
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entity Pipeline_pb is
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generic (
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--@ Number of pipeline stages
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G_PipelineStages : integer := 10;
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--@ Number of pipeline stages inside each module
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G_PipelineStages : integer := 2;
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--@ Data width
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G_Width : integer := 32;
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G_Width : integer := 8;
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--@ Register balancing attribute<br>
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--@ - "no" : No register balancing <br>
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--@ - "yes": Register balancing in both directions <br>
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--@ - "forward": Moves a set of FFs at the inputs of a LUT to a single FF at its output. <br>
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--@ - "backward": Moves a single FF at the output of a LUT to a set of FFs at its inputs.
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G_RegisterBalancing : string := "yes"
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G_RegisterBalancing : string := "yes";
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--@ Enable pipeline buffer
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--@ - true : Use pipeline buffer
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--@ - false : Direct connection (bypass)
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G_EnablePipelineBuffer : boolean := true;
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--@ How many Pipeline modules shall be chained?
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G_PipelineModules : integer := 250;
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--@ Enable chip enable signal
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G_Enable_CE : boolean := false;
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--@ Enable reset signal
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G_Enable_RST : boolean := false
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);
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port (
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I_CLK : in std_logic;
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I_RST : in std_logic;
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I_CE : in std_logic;
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---
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I_Data : in std_logic_vector(G_Width - 1 downto 0);
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I_Valid : in std_logic;
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O_Ready : out std_logic;
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---
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O_Data : out std_logic_vector(G_Width - 1 downto 0);
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O_Valid : out std_logic;
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I_Ready : in std_logic
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@@ -36,119 +48,116 @@ entity Pipeline_pb is
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end entity Pipeline_pb;
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architecture RTL of Pipeline_pb is
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-- Keep attribute: Prevents the synthesis tool from removing the entity if is "true".
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---------------------------------------------------------------------------
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-- Attribute helpers
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---------------------------------------------------------------------------
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attribute keep : string;
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-- IOB attribute: Attaches the FF to the IOB if is "true".
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attribute IOB : string;
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-- General Interace
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signal R_RST : std_logic;
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signal R_CE : std_logic;
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-- Attribute
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---------------------------------------------------------------------------
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-- Bench‐wrapper FFs (synchronous IO)
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---------------------------------------------------------------------------
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signal R_RST : std_logic := '0';
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signal R_CE : std_logic := '1';
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attribute keep of R_RST, R_CE : signal is "true";
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attribute IOB of R_RST, R_CE : signal is "false";
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-- Input Interface
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signal R_DataIn : std_logic_vector(G_Width - 1 downto 0);
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signal R_ValidIn : std_logic;
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signal R_ReadyOut : std_logic;
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-- Attribute
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attribute keep of R_DataIn, R_ValidIn, R_ReadyOut : signal is "true";
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attribute IOB of R_DataIn, R_ValidIn, R_ReadyOut : signal is "false";
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signal R_DataIn : std_logic_vector(G_Width-1 downto 0);
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signal R_ValidIn : std_logic;
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attribute keep of R_DataIn, R_ValidIn : signal is "true";
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attribute IOB of R_DataIn, R_ValidIn : signal is "false";
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-- Output Interface
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signal R_DataOut : std_logic_vector(G_Width - 1 downto 0);
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signal R_DataOut : std_logic_vector(G_Width-1 downto 0);
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signal R_ValidOut : std_logic;
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signal R_ReadyIn : std_logic;
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-- Attribute
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attribute keep of R_DataOut, R_ValidOut, R_ReadyIn : signal is "true";
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attribute IOB of R_DataOut, R_ValidOut, R_ReadyIn : signal is "false";
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signal C_Pipeline0Enable : std_logic;
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signal C_Pipeline1Enable : std_logic;
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---------------------------------------------------------------------------
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-- Chaining arrays (sentinel element @0 and @G_PipelineModules)
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---------------------------------------------------------------------------
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type T_DataArray is array(0 to G_PipelineModules) of std_logic_vector(G_Width-1 downto 0);
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signal S_Data : T_DataArray;
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signal S_Valid : std_logic_vector(0 to G_PipelineModules);
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signal S_Ready : std_logic_vector(0 to G_PipelineModules);
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signal R_Valid : std_logic;
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signal R_Ready : std_logic;
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signal R_Data : std_logic_vector(G_Width - 1 downto 0);
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begin
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GEN_Enable_CE : if G_Enable_CE = true generate
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process(I_CLK)
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begin
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if rising_edge(I_CLK) then
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R_CE <= I_CE;
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end if;
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end process;
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end generate GEN_Enable_CE;
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BenchmarkEnvironmentFFs : process (I_CLK)
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GEN_Enable_RST : if G_Enable_RST = true generate
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process(I_CLK)
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begin
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if rising_edge(I_CLK) then
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R_RST <= I_RST;
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end if;
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end process;
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end generate GEN_Enable_RST;
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-----------------------------------------------------------------------
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-- Wrapper FFs: register all top‑level ports once for fair timing
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-----------------------------------------------------------------------
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BenchFF : process(I_CLK)
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begin
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if rising_edge(I_CLK) then
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-- General Interace
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R_RST <= I_RST;
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R_CE <= I_CE;
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-- Input Interface
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R_DataIn <= I_Data;
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R_ValidIn <= I_Valid;
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O_Ready <= R_ReadyOut;
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-- Output Interface
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O_Data <= R_DataOut;
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O_Valid <= R_ValidOut;
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R_ReadyIn <= I_Ready;
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--- Register inputs
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R_DataIn <= I_Data;
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R_ValidIn <= I_Valid;
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O_Ready <= S_Ready(0);
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--- Register outputs
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R_DataOut <= S_Data (G_PipelineModules);
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R_ValidOut <= S_Valid(G_PipelineModules);
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R_ReadyIn <= I_Ready;
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end if;
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end process;
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PipelineControllerIn : entity work.PipelineController
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generic map(
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G_PipelineStages => G_PipelineStages,
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G_ResetActiveAt => '1'
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)
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port map(
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I_CLK => I_CLK,
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I_RST => R_RST,
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I_CE => R_CE,
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O_Enable => C_Pipeline0Enable,
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I_Valid => R_ValidIn,
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O_Ready => R_ReadyOut,
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O_Valid => R_Valid,
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I_Ready => R_Ready
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);
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O_Data <= R_DataOut;
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O_Valid <= R_ValidOut;
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PipelineRegisterIn : entity work.PipelineRegister
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generic map(
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G_PipelineStages => G_PipelineStages,
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G_Width => G_Width,
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G_RegisterBalancing => G_RegisterBalancing
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)
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port map(
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I_CLK => I_CLK,
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I_Enable => C_Pipeline0Enable,
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I_Data => R_DataIn,
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O_Data => R_Data
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);
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-----------------------------------------------------------------------
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-- Bind sentinel 0 with registered inputs
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-----------------------------------------------------------------------
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S_Data (0) <= R_DataIn;
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S_Valid(0) <= R_ValidIn;
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---------
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-----------------------------------------------------------------------
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-- Bind last sentinel with registered outputs
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-----------------------------------------------------------------------
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S_Ready(G_PipelineModules) <= R_ReadyIn;
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PipelineControllerOut : entity work.PipelineController
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generic map(
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G_PipelineStages => G_PipelineStages,
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G_ResetActiveAt => '1'
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)
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port map(
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I_CLK => I_CLK,
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I_RST => R_RST,
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I_CE => R_CE,
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O_Enable => C_Pipeline1Enable,
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I_Valid => R_Valid,
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O_Ready => R_Ready,
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O_Valid => R_ValidOut,
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I_Ready => R_ReadyIn
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);
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-----------------------------------------------------------------------
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-- Generate N pipeline modules in series
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-----------------------------------------------------------------------
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gen_modules : for i in 0 to G_PipelineModules-1 generate
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PipelineRegisterOut : entity work.PipelineRegister
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generic map(
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G_PipelineStages => G_PipelineStages,
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G_Width => G_Width,
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G_RegisterBalancing => G_RegisterBalancing
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)
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port map(
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I_CLK => I_CLK,
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I_Enable => C_Pipeline1Enable,
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I_Data => R_Data,
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O_Data => R_DataOut
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);
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P_MOD : entity work.Pipeline_pb_Module
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generic map(
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G_PipelineStages => G_PipelineStages,
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G_Width => G_Width,
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G_RegisterBalancing => G_RegisterBalancing,
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G_EnablePipelineBuffer => G_EnablePipelineBuffer
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)
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port map(
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I_CLK => I_CLK,
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I_RST => R_RST,
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I_CE => R_CE,
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-- Up‑stream side
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I_Data => S_Data (i),
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I_Valid => S_Valid(i),
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O_Ready => S_Ready(i),
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-- Down‑stream side
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O_Data => S_Data (i+1),
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O_Valid => S_Valid(i+1),
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I_Ready => S_Ready(i+1)
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);
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end generate gen_modules;
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end architecture RTL;
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123
src/Pipeline_pb_Module.vhd
Normal file
123
src/Pipeline_pb_Module.vhd
Normal file
@@ -0,0 +1,123 @@
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--@ Performance Benchmarking Environment
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--@ This file is a wrapper for the module which is to be tested
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--@ and capsulates the module with flip-flops to create a synchronous
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--@ interface for the module. This is necessary to test the synthesis
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--@ results of the module.
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.math_real.all;
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entity Pipeline_pb_Module is
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generic (
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--@ Number of pipeline stages
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G_PipelineStages : integer := 10;
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--@ Data width
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G_Width : integer := 32;
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--@ Register balancing attribute<br>
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--@ - "no" : No register balancing <br>
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--@ - "yes": Register balancing in both directions <br>
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--@ - "forward": Moves a set of FFs at the inputs of a LUT to a single FF at its output. <br>
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--@ - "backward": Moves a single FF at the output of a LUT to a set of FFs at its inputs.
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G_RegisterBalancing : string := "no";
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--@ Enable pipeline buffer
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--@ - true : Use pipeline buffer
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--@ - false : Direct connection (bypass)
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G_EnablePipelineBuffer : boolean := false
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);
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port (
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I_CLK : in std_logic;
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I_RST : in std_logic;
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I_CE : in std_logic;
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I_Data : in std_logic_vector(G_Width - 1 downto 0);
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I_Valid : in std_logic;
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O_Ready : out std_logic;
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O_Data : out std_logic_vector(G_Width - 1 downto 0);
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O_Valid : out std_logic;
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I_Ready : in std_logic
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);
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end entity Pipeline_pb_Module;
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architecture RTL of Pipeline_pb_Module is
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signal C_Pipeline0Enable : std_logic;
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signal C_PipelineBufferEnable : std_logic_vector(1 downto 0) := (others => '0');
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signal R_Valid : std_logic;
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signal R_Ready : std_logic;
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signal R_Data : std_logic_vector(G_Width - 1 downto 0);
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signal C_Data : std_logic_vector(G_Width - 1 downto 0);
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begin
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PipelineControllerIn : entity work.PipelineController
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generic map(
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G_PipelineStages => G_PipelineStages,
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G_ResetActiveAt => '1'
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)
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port map(
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I_CLK => I_CLK,
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I_RST => I_RST,
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I_CE => I_CE,
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O_Enable => C_Pipeline0Enable,
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I_Valid => I_Valid,
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O_Ready => O_Ready,
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O_Valid => R_Valid,
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I_Ready => R_Ready
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);
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PipelineRegisterIn : entity work.PipelineRegister
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generic map(
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G_PipelineStages => G_PipelineStages,
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G_Width => G_Width,
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G_RegisterBalancing => G_RegisterBalancing
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)
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port map(
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I_CLK => I_CLK,
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I_Enable => C_Pipeline0Enable,
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I_Data => I_Data,
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O_Data => R_Data
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);
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---------
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C_Data <= std_logic_vector(unsigned(R_Data) + 3); -- Example operation, can be replaced with actual logic
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---------
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-- Pipeline Buffer Generation based on G_EnablePipelineBuffer
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gen_pipeline_buffer : if G_EnablePipelineBuffer generate
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PipelineBufferController : entity work.PipelineBufferController
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generic map(
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G_ResetActiveAt => '1'
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)
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port map(
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I_CLK => I_CLK,
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I_RST => I_RST,
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I_CE => I_CE,
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O_Enable => C_PipelineBufferEnable,
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I_Valid => R_Valid,
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O_Ready => R_Ready,
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O_Valid => O_Valid,
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I_Ready => I_Ready
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);
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PipelineBuffer : entity work.PipelineBuffer
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generic map(
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G_Width => G_Width
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)
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port map(
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I_CLK => I_CLK,
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I_Enable => C_PipelineBufferEnable,
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I_Data => C_Data,
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O_Data => O_Data
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);
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end generate gen_pipeline_buffer;
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-- Direct connection when pipeline buffer is disabled
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gen_direct_connection : if not G_EnablePipelineBuffer generate
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-- Direct signal connections (bypass pipeline buffer)
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O_Valid <= R_Valid;
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O_Data <= R_Data;
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R_Ready <= I_Ready;
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end generate gen_direct_connection;
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end architecture RTL;
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