HDL/Pipeline-AXI-Handshake
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feat: implements pipelined module chaining for performance

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- Introduces a pipelined module and top-level wrapper for
  performance benchmarking.
- Chains multiple pipeline modules in series to increase throughput.
- Adds generics to control pipeline depth, data width, and
  register balancing.
- Includes optional CE/RST enables and pipeline buffer.
This commit is contained in:
0xMax42
2025-07-11 10:05:02 +00:00
parent 96833c0f77
commit 88753b62f4
2 changed files with 226 additions and 94 deletions
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197
src/Pipeline_pb.vhd
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@@ -11,24 +11,36 @@ use ieee.math_real.all;
entity Pipeline_pb is entity Pipeline_pb is
generic ( generic (
--@ Number of pipeline stages --@ Number of pipeline stages inside each module
G_PipelineStages : integer := 10; G_PipelineStages : integer := 2;
--@ Data width --@ Data width
G_Width : integer := 32; G_Width : integer := 8;
--@ Register balancing attribute<br> --@ Register balancing attribute<br>
--@ - "no" : No register balancing <br> --@ - "no" : No register balancing <br>
--@ - "yes": Register balancing in both directions <br> --@ - "yes": Register balancing in both directions <br>
--@ - "forward": Moves a set of FFs at the inputs of a LUT to a single FF at its output. <br> --@ - "forward": Moves a set of FFs at the inputs of a LUT to a single FF at its output. <br>
--@ - "backward": Moves a single FF at the output of a LUT to a set of FFs at its inputs. --@ - "backward": Moves a single FF at the output of a LUT to a set of FFs at its inputs.
G_RegisterBalancing : string := "yes" G_RegisterBalancing : string := "yes";
--@ Enable pipeline buffer
--@ - true : Use pipeline buffer
--@ - false : Direct connection (bypass)
G_EnablePipelineBuffer : boolean := true;
--@ How many Pipeline modules shall be chained?
G_PipelineModules : integer := 250;
--@ Enable chip enable signal
G_Enable_CE : boolean := false;
--@ Enable reset signal
G_Enable_RST : boolean := false
); );
port ( port (
I_CLK : in std_logic; I_CLK : in std_logic;
I_RST : in std_logic; I_RST : in std_logic;
I_CE : in std_logic; I_CE : in std_logic;
---
I_Data : in std_logic_vector(G_Width - 1 downto 0); I_Data : in std_logic_vector(G_Width - 1 downto 0);
I_Valid : in std_logic; I_Valid : in std_logic;
O_Ready : out std_logic; O_Ready : out std_logic;
---
O_Data : out std_logic_vector(G_Width - 1 downto 0); O_Data : out std_logic_vector(G_Width - 1 downto 0);
O_Valid : out std_logic; O_Valid : out std_logic;
I_Ready : in std_logic I_Ready : in std_logic
@@ -36,119 +48,116 @@ entity Pipeline_pb is
end entity Pipeline_pb; end entity Pipeline_pb;
architecture RTL of Pipeline_pb is architecture RTL of Pipeline_pb is
-- Keep attribute: Prevents the synthesis tool from removing the entity if is "true". ---------------------------------------------------------------------------
-- Attribute helpers
---------------------------------------------------------------------------
attribute keep : string; attribute keep : string;
-- IOB attribute: Attaches the FF to the IOB if is "true".
attribute IOB : string; attribute IOB : string;
-- General Interace ---------------------------------------------------------------------------
signal R_RST : std_logic; -- Bench‐wrapper FFs (synchronous IO)
signal R_CE : std_logic; ---------------------------------------------------------------------------
-- Attribute signal R_RST : std_logic := '0';
signal R_CE : std_logic := '1';
attribute keep of R_RST, R_CE : signal is "true"; attribute keep of R_RST, R_CE : signal is "true";
attribute IOB of R_RST, R_CE : signal is "false"; attribute IOB of R_RST, R_CE : signal is "false";
-- Input Interface signal R_DataIn : std_logic_vector(G_Width-1 downto 0);
signal R_DataIn : std_logic_vector(G_Width - 1 downto 0); signal R_ValidIn : std_logic;
signal R_ValidIn : std_logic; attribute keep of R_DataIn, R_ValidIn : signal is "true";
signal R_ReadyOut : std_logic; attribute IOB of R_DataIn, R_ValidIn : signal is "false";
-- Attribute
attribute keep of R_DataIn, R_ValidIn, R_ReadyOut : signal is "true";
attribute IOB of R_DataIn, R_ValidIn, R_ReadyOut : signal is "false";
-- Output Interface signal R_DataOut : std_logic_vector(G_Width-1 downto 0);
signal R_DataOut : std_logic_vector(G_Width - 1 downto 0);
signal R_ValidOut : std_logic; signal R_ValidOut : std_logic;
signal R_ReadyIn : std_logic; signal R_ReadyIn : std_logic;
-- Attribute
attribute keep of R_DataOut, R_ValidOut, R_ReadyIn : signal is "true"; attribute keep of R_DataOut, R_ValidOut, R_ReadyIn : signal is "true";
attribute IOB of R_DataOut, R_ValidOut, R_ReadyIn : signal is "false"; attribute IOB of R_DataOut, R_ValidOut, R_ReadyIn : signal is "false";
signal C_Pipeline0Enable : std_logic; ---------------------------------------------------------------------------
signal C_Pipeline1Enable : std_logic; -- Chaining arrays (sentinel element @0 and @G_PipelineModules)
---------------------------------------------------------------------------
type T_DataArray is array(0 to G_PipelineModules) of std_logic_vector(G_Width-1 downto 0);
signal S_Data : T_DataArray;
signal S_Valid : std_logic_vector(0 to G_PipelineModules);
signal S_Ready : std_logic_vector(0 to G_PipelineModules);
signal R_Valid : std_logic;
signal R_Ready : std_logic;
signal R_Data : std_logic_vector(G_Width - 1 downto 0);
begin begin
GEN_Enable_CE : if G_Enable_CE = true generate
process(I_CLK)
begin
if rising_edge(I_CLK) then
R_CE <= I_CE;
end if;
end process;
end generate GEN_Enable_CE;
BenchmarkEnvironmentFFs : process (I_CLK) GEN_Enable_RST : if G_Enable_RST = true generate
process(I_CLK)
begin
if rising_edge(I_CLK) then
R_RST <= I_RST;
end if;
end process;
end generate GEN_Enable_RST;
-----------------------------------------------------------------------
-- Wrapper FFs: register all top‑level ports once for fair timing
-----------------------------------------------------------------------
BenchFF : process(I_CLK)
begin begin
if rising_edge(I_CLK) then if rising_edge(I_CLK) then
-- General Interace --- Register inputs
R_RST <= I_RST; R_DataIn <= I_Data;
R_CE <= I_CE; R_ValidIn <= I_Valid;
O_Ready <= S_Ready(0);
-- Input Interface --- Register outputs
R_DataIn <= I_Data; R_DataOut <= S_Data (G_PipelineModules);
R_ValidIn <= I_Valid; R_ValidOut <= S_Valid(G_PipelineModules);
O_Ready <= R_ReadyOut; R_ReadyIn <= I_Ready;
-- Output Interface
O_Data <= R_DataOut;
O_Valid <= R_ValidOut;
R_ReadyIn <= I_Ready;
end if; end if;
end process; end process;
PipelineControllerIn : entity work.PipelineController O_Data <= R_DataOut;
generic map( O_Valid <= R_ValidOut;
G_PipelineStages => G_PipelineStages,
G_ResetActiveAt => '1'
)
port map(
I_CLK => I_CLK,
I_RST => R_RST,
I_CE => R_CE,
O_Enable => C_Pipeline0Enable,
I_Valid => R_ValidIn,
O_Ready => R_ReadyOut,
O_Valid => R_Valid,
I_Ready => R_Ready
);
PipelineRegisterIn : entity work.PipelineRegister -----------------------------------------------------------------------
generic map( -- Bind sentinel 0 with registered inputs
G_PipelineStages => G_PipelineStages, -----------------------------------------------------------------------
G_Width => G_Width, S_Data (0) <= R_DataIn;
G_RegisterBalancing => G_RegisterBalancing S_Valid(0) <= R_ValidIn;
)
port map(
I_CLK => I_CLK,
I_Enable => C_Pipeline0Enable,
I_Data => R_DataIn,
O_Data => R_Data
);
--------- -----------------------------------------------------------------------
-- Bind last sentinel with registered outputs
-----------------------------------------------------------------------
S_Ready(G_PipelineModules) <= R_ReadyIn;
PipelineControllerOut : entity work.PipelineController -----------------------------------------------------------------------
generic map( -- Generate N pipeline modules in series
G_PipelineStages => G_PipelineStages, -----------------------------------------------------------------------
G_ResetActiveAt => '1' gen_modules : for i in 0 to G_PipelineModules-1 generate
)
port map(
I_CLK => I_CLK,
I_RST => R_RST,
I_CE => R_CE,
O_Enable => C_Pipeline1Enable,
I_Valid => R_Valid,
O_Ready => R_Ready,
O_Valid => R_ValidOut,
I_Ready => R_ReadyIn
);
PipelineRegisterOut : entity work.PipelineRegister P_MOD : entity work.Pipeline_pb_Module
generic map( generic map(
G_PipelineStages => G_PipelineStages, G_PipelineStages => G_PipelineStages,
G_Width => G_Width, G_Width => G_Width,
G_RegisterBalancing => G_RegisterBalancing G_RegisterBalancing => G_RegisterBalancing,
) G_EnablePipelineBuffer => G_EnablePipelineBuffer
port map( )
I_CLK => I_CLK, port map(
I_Enable => C_Pipeline1Enable, I_CLK => I_CLK,
I_Data => R_Data, I_RST => R_RST,
O_Data => R_DataOut I_CE => R_CE,
); -- Up‑stream side
I_Data => S_Data (i),
I_Valid => S_Valid(i),
O_Ready => S_Ready(i),
-- Down‑stream side
O_Data => S_Data (i+1),
O_Valid => S_Valid(i+1),
I_Ready => S_Ready(i+1)
);
end generate gen_modules;
end architecture RTL; end architecture RTL;

123
src/Pipeline_pb_Module.vhd Normal file
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@@ -0,0 +1,123 @@
--@ Performance Benchmarking Environment
--@ This file is a wrapper for the module which is to be tested
--@ and capsulates the module with flip-flops to create a synchronous
--@ interface for the module. This is necessary to test the synthesis
--@ results of the module.
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.math_real.all;
entity Pipeline_pb_Module is
generic (
--@ Number of pipeline stages
G_PipelineStages : integer := 10;
--@ Data width
G_Width : integer := 32;
--@ Register balancing attribute<br>
--@ - "no" : No register balancing <br>
--@ - "yes": Register balancing in both directions <br>
--@ - "forward": Moves a set of FFs at the inputs of a LUT to a single FF at its output. <br>
--@ - "backward": Moves a single FF at the output of a LUT to a set of FFs at its inputs.
G_RegisterBalancing : string := "no";
--@ Enable pipeline buffer
--@ - true : Use pipeline buffer
--@ - false : Direct connection (bypass)
G_EnablePipelineBuffer : boolean := false
);
port (
I_CLK : in std_logic;
I_RST : in std_logic;
I_CE : in std_logic;
I_Data : in std_logic_vector(G_Width - 1 downto 0);
I_Valid : in std_logic;
O_Ready : out std_logic;
O_Data : out std_logic_vector(G_Width - 1 downto 0);
O_Valid : out std_logic;
I_Ready : in std_logic
);
end entity Pipeline_pb_Module;
architecture RTL of Pipeline_pb_Module is
signal C_Pipeline0Enable : std_logic;
signal C_PipelineBufferEnable : std_logic_vector(1 downto 0) := (others => '0');
signal R_Valid : std_logic;
signal R_Ready : std_logic;
signal R_Data : std_logic_vector(G_Width - 1 downto 0);
signal C_Data : std_logic_vector(G_Width - 1 downto 0);
begin
PipelineControllerIn : entity work.PipelineController
generic map(
G_PipelineStages => G_PipelineStages,
G_ResetActiveAt => '1'
)
port map(
I_CLK => I_CLK,
I_RST => I_RST,
I_CE => I_CE,
O_Enable => C_Pipeline0Enable,
I_Valid => I_Valid,
O_Ready => O_Ready,
O_Valid => R_Valid,
I_Ready => R_Ready
);
PipelineRegisterIn : entity work.PipelineRegister
generic map(
G_PipelineStages => G_PipelineStages,
G_Width => G_Width,
G_RegisterBalancing => G_RegisterBalancing
)
port map(
I_CLK => I_CLK,
I_Enable => C_Pipeline0Enable,
I_Data => I_Data,
O_Data => R_Data
);
---------
C_Data <= std_logic_vector(unsigned(R_Data) + 3); -- Example operation, can be replaced with actual logic
---------
-- Pipeline Buffer Generation based on G_EnablePipelineBuffer
gen_pipeline_buffer : if G_EnablePipelineBuffer generate
PipelineBufferController : entity work.PipelineBufferController
generic map(
G_ResetActiveAt => '1'
)
port map(
I_CLK => I_CLK,
I_RST => I_RST,
I_CE => I_CE,
O_Enable => C_PipelineBufferEnable,
I_Valid => R_Valid,
O_Ready => R_Ready,
O_Valid => O_Valid,
I_Ready => I_Ready
);
PipelineBuffer : entity work.PipelineBuffer
generic map(
G_Width => G_Width
)
port map(
I_CLK => I_CLK,
I_Enable => C_PipelineBufferEnable,
I_Data => C_Data,
O_Data => O_Data
);
end generate gen_pipeline_buffer;
-- Direct connection when pipeline buffer is disabled
gen_direct_connection : if not G_EnablePipelineBuffer generate
-- Direct signal connections (bypass pipeline buffer)
O_Valid <= R_Valid;
O_Data <= R_Data;
R_Ready <= I_Ready;
end generate gen_direct_connection;
end architecture RTL;