HDL/Pipeline-AXI-Handshake
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Standardizes formatting and adds output signal

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Adjusts entity and architecture formatting for consistency, aligning spacing and indentation across declarations and constants.

Adds `O_MUX_Select` output signal to indicate routing decision, improving functionality and clarity of the module.
This commit is contained in:
0xMax42
2025-04-24 18:29:53 +00:00
parent 3a588948a6
commit 454172e91c
1 changed files with 30 additions and 25 deletions
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5
src/PipelineSwitch.vhd
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@@ -39,6 +39,9 @@ entity PipelineSwitch is
O_Ready : out std_logic := '0'; O_Ready : out std_logic := '0';
--@ @end --@ @end
--@ If `1`, route to `Selected` output; if `0`, route to `Default` output.
O_MUX_Select : out std_logic := '0';
--@ @virtualbus AXI-Flags-Out @dir Out Output interface for unmatched routing --@ @virtualbus AXI-Flags-Out @dir Out Output interface for unmatched routing
--@ Activated when the comparison **fails**. --@ Activated when the comparison **fails**.
--@ AXI-like valid; (**Synchronous**, **Active high**) --@ AXI-like valid; (**Synchronous**, **Active high**)
@@ -189,4 +192,6 @@ begin
end if; end if;
end process; end process;
O_MUX_Select <= C_ShouldRouteToSelected;
end architecture; end architecture;