Max P
dfc19b739b
The Generic Counter VHDL module has been added under `src`, providing a configurable digital counter with synchronous reset, clock enable, set priority, over/underflow flag, and up/down counting capabilities. This addition includes detailed documentation and a waveform for simulation purposes, signifying an emphasis on maintainability and verification via the included Testbench, which has passed simulation.
4 lines
93 B
Plaintext
4 lines
93 B
Plaintext
[submodule "build"]
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path = build
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url = https://github.com/PxaMMaxP/Xilinx-ISE-Makefile.git
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