Introduced a new VHDL testbench for the GenericCounter component, complete with initial signal declarations, a clock process, and a stimulus process to emulate different scenarios and edge cases. The inclusion of generics and port mappings ensures the testbench's flexibility to simulate counter behavior under various conditions. Accompanying the testbench, a wave configuration file has been added to aid in simulation analysis, allowing for visualization and easier debugging of the component's states during simulation runs.
