Updated the SVG in the documentation for better readability and visual appeal. Added a white background rectangle to ensure consistent visibility across different backgrounds.
Enhanced the GenericCounter VHDL module by adding a comprehensive set of features, including synchronous reset, clock enable, configurable counting direction, over- and underflow flags, and lookahead value. Introduced detailed project documentation, including a descriptive README, waveform diagrams in both SVG and JSON format, and a UCF constraints file specifying clock settings.
