Add GenericCounter VHDL module
The Generic Counter VHDL module has been added under `src`, providing a configurable digital counter with synchronous reset, clock enable, set priority, over/underflow flag, and up/down counting capabilities. This addition includes detailed documentation and a waveform for simulation purposes, signifying an emphasis on maintainability and verification via the included Testbench, which has passed simulation.
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[submodule "build"]
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path = build
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url = ssh://git@github.com:PxaMMaxP/Xilinx-ISE-Makefile.git
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url = https://github.com/PxaMMaxP/Xilinx-ISE-Makefile.git
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build
Submodule
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build
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Submodule build added at d7eebb6517
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src/GenericCounter.vhd
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183
src/GenericCounter.vhd
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----------------------------------------------------------------------------------
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--@ - Name: Generic Counter <br>
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--@ - Version: 0.0.2 <br>
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--@ - Author: __Maximilian Passarello ([Blog](mpassarello.de))__ <br>
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--@ - License: [MIT](LICENSE) <br>
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--@
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--@ Generic Counter with the following features:
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--@ - **Without Output Register**
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--@ - Look ahead value (configurable per generic)
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--@ - Synchronous reset
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--@ - Clock enable
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--@ - Set with priority over the `CountEnable`
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--@ - Over- and Underflow flag
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--@ - Configurable width
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--@ - Configurable initial value
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--@ - Configurable reset value
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--@ - Configurable counting direction (Up and Down counting)
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--@ ## History
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--@ - 0.0.1 (2024-03-15) Initial version
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--@ - 0.0.2 (2024-03-16) Added Testbench. Simulation passed.
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----------------------------------------------------------------------------------
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--@ ## Waveform
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--@ {
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--@ "signal": [
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--@ [
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--@ "General",
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--@ {
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--@ "name": "CLK",
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--@ "wave": "P.....|........",
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--@ "node": "0123456789abcde",
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--@ "period": 1
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--@ },
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--@ {
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--@ "name": "RST",
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--@ "wave": "10....|.....10."
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--@ },
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--@ {
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--@ "name": "CE",
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--@ "wave": "0.1...|........"
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--@ }
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--@ ],
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--@ [
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--@ "Set",
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--@ {
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--@ "name": "Set",
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--@ "wave": "0.....|..10...."
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--@ },
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--@ {
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--@ "name": "SetValue",
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--@ "wave": "x.....|..8x....",
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--@ "data": [
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--@ "5"
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--@ ]
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--@ }
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--@ ],
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--@ [
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--@ "Counter",
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--@ {
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--@ "name": "CountEnable",
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--@ "wave": "0..1..|.......0"
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--@ },
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--@ {
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--@ "name": "CounterValue",
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--@ "wave": "4..777|77777777",
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--@ "data": "0 1 2 3 15 0 5 6 7 8 1 1"
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--@ },
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--@ {
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--@ "name": "LookAheadValue",
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--@ "wave": "4..777|77777777",
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--@ "data": "1 2 3 4 0 1 6 7 8 9 2 2"
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--@ }
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--@ ],
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--@ [
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--@ "Flags",
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--@ {
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--@ "name": "OverUnderflow",
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--@ "wave": "0.....|.10....."
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--@ }
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--@ ]
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--@ ],
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--@ "config": {
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--@ "hscale": 1
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--@ },
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--@ "head": {
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--@ "text": "<b>Generic Counter</b>"
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--@ },
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--@ "foot": {
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--@ "text": "RST Value = 0"
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--@ }
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--@ }
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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use ieee.math_real.all;
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entity GenericCounter is
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generic (
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--@ Width of the counter
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Width : integer := 4;
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--@ Initial value of the counter
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InitialValue : integer := 0;
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--@ Reset value of the counter
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ResetValue : integer := 0;
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--@ Counting direction: "UP" or "DOWN"
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CountingDirection : string := "UP";
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--@ Look ahead value
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LookAhead : integer := 0
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);
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port (
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--@ Clock input; rising edge
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CLK : in std_logic;
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--@ Reset input; active high; synchronous
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RST : in std_logic;
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--@ Clock enable; active high
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CE : in std_logic;
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--@ Count enable; active high
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CountEnable : in std_logic;
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--@ Counter Value
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CounterValue : out std_logic_vector(Width - 1 downto 0);
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--@ Look ahead value
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LookAheadValue : out std_logic_vector(Width - 1 downto 0);
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--@ Set with priority over the `CountEnable`
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Set : in std_logic;
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--@ If set is high, the counter will be set to SetValue
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SetValue : in std_logic_vector(Width - 1 downto 0);
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--@ Over- and Underflow flag
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OverUnderflow : out std_logic
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);
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end entity GenericCounter;
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architecture RTL of GenericCounter is
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function CountingStep(BinaryValue : unsigned; Step : integer := 1)
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return unsigned is
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begin
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if CountingDirection = "UP" then
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return BinaryValue + Step;
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else
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return BinaryValue - Step;
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end if;
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end function CountingStep;
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signal R_Counter : unsigned(Width - 1 downto 0) := to_unsigned(InitialValue, Width);
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signal C_NextCounter : unsigned(Width - 1 downto 0) := to_unsigned(InitialValue, Width);
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signal C_LookAhead : unsigned(Width - 1 downto 0) := to_unsigned(InitialValue + LookAhead, Width);
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signal C_OverUnderflow : std_logic;
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begin
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process (CLK)
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begin
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if rising_edge(CLK) then
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if RST = '1' then
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R_Counter <= to_unsigned(ResetValue, Width);
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elsif CE = '1' then
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R_Counter <= C_NextCounter;
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end if;
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end if;
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end process;
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Counting : process (R_Counter, CountEnable, Set, SetValue)
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variable V_OverUnderflow : unsigned(Width downto 0);
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begin
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V_OverUnderflow := CountingStep("0" & R_Counter);
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if Set = '1' then
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C_NextCounter <= unsigned(SetValue);
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C_LookAhead <= CountingStep(unsigned(SetValue), LookAhead);
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C_OverUnderflow <= '0';
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elsif CountEnable = '1' then
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C_NextCounter <= V_OverUnderflow(Width - 1 downto 0);
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C_LookAhead <= CountingStep(R_Counter, 1 + LookAhead);
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C_OverUnderflow <= V_OverUnderflow(Width);
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else
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C_NextCounter <= R_Counter;
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C_LookAhead <= CountingStep(R_Counter, LookAhead);
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C_OverUnderflow <= '0';
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end if;
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end process;
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LookAheadValue <= std_logic_vector(C_LookAhead);
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CounterValue <= std_logic_vector(C_NextCounter);
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OverUnderflow <= C_OverUnderflow;
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end architecture RTL;
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