HDL/GenericCounter
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Add GenericCounter VHDL module

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The Generic Counter VHDL module has been added under `src`, providing a configurable digital counter with synchronous reset, clock enable, set priority, over/underflow flag, and up/down counting capabilities. This addition includes detailed documentation and a waveform for simulation purposes, signifying an emphasis on maintainability and verification via the included Testbench, which has passed simulation.
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0xMax42
2024-03-16 14:42:46 +01:00
parent 09e5befeac
commit dfc19b739b
3 changed files with 185 additions and 1 deletions
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.gitmodules vendored
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@@ -1,3 +1,3 @@
[submodule "build"]
path = build
url = ssh://git@github.com:PxaMMaxP/Xilinx-ISE-Makefile.git
url = https://github.com/PxaMMaxP/Xilinx-ISE-Makefile.git