diff --git a/tests/GenericCounter_tb.vhd b/tests/GenericCounter_tb.vhd
new file mode 100644
index 0000000..c91a802
--- /dev/null
+++ b/tests/GenericCounter_tb.vhd
@@ -0,0 +1,110 @@
+-- VHDL Testbench for GenericCounter
+library ieee;
+use ieee.std_logic_1164.all;
+
+entity GenericCounter_tb is
+end GenericCounter_tb;
+
+architecture behavior of GenericCounter_tb is
+    -- Component Declaration for the Unit Under Test (UUT)
+    component GenericCounter
+        generic (
+            Width             : integer := 4;
+            InitialValue      : integer := 0;
+            ResetValue        : integer := 0;
+            CountingDirection : string  := "UP";
+            LookAhead         : integer := 0
+        );
+        port (
+            CLK            : in std_logic;
+            RST            : in std_logic;
+            CE             : in std_logic;
+            CountEnable    : in std_logic;
+            CounterValue   : out std_logic_vector(Width - 1 downto 0);
+            LookAheadValue : out std_logic_vector(Width - 1 downto 0);
+            Set            : in std_logic;
+            SetValue       : in std_logic_vector(Width - 1 downto 0);
+            OverUnderflow  : out std_logic
+        );
+    end component;
+
+    -- Inputs
+    signal CLK         : std_logic                    := '0';
+    signal RST         : std_logic                    := '0';
+    signal CE          : std_logic                    := '0';
+    signal CountEnable : std_logic                    := '0';
+    signal Set         : std_logic                    := '0';
+    signal SetValue    : std_logic_vector(3 downto 0) := (others => '0');
+
+    --Outputs
+    signal CounterValue   : std_logic_vector(3 downto 0);
+    signal LookAheadValue : std_logic_vector(3 downto 0);
+    signal OverUnderflow  : std_logic;
+
+    -- Clock period definitions
+    constant CLK_period : time := 10 ns;
+
+begin
+    -- Instantiate the Unit Under Test (UUT)
+    uut : component GenericCounter
+        generic map(
+            Width             => 4,
+            InitialValue      => 0,
+            ResetValue        => 0,
+            CountingDirection => "UP",
+            LookAhead         => 1
+        )
+        port map(
+            CLK            => CLK,
+            RST            => RST,
+            CE             => CE,
+            CountEnable    => CountEnable,
+            CounterValue   => CounterValue,
+            LookAheadValue => LookAheadValue,
+            Set            => Set,
+            SetValue       => SetValue,
+            OverUnderflow  => OverUnderflow
+        );
+
+        -- Clock process definitions
+        CLK_process : process
+        begin
+            CLK <= '0';
+            wait for CLK_period/2;
+            CLK <= '1';
+            wait for CLK_period/2;
+        end process;
+
+        -- Testbench Statements
+        stim_proc : process
+        begin
+            -- Initialize Inputs
+            RST <= '1';
+            wait for CLK_period * 1;
+            RST <= '0';
+            CE  <= '1';
+
+            -- Add stimulus here
+            CountEnable <= '0';
+            wait for CLK_period * 5;
+
+            -- Add stimulus here
+            CountEnable <= '1';
+            wait for CLK_period * 5;
+
+            -- Set operation
+            Set      <= '1';
+            SetValue <= "1010";
+            wait for CLK_period * 1;
+            Set <= '0';
+
+            -- Additional stimulus
+            wait for CLK_period * 10;
+            RST <= '1';
+            wait for CLK_period * 1;
+            RST <= '0';
+
+            wait;
+        end process;
+
+    end behavior;
diff --git a/tests/GenericCounter_tb.wcfg b/tests/GenericCounter_tb.wcfg
new file mode 100644
index 0000000..9f99a35
--- /dev/null
+++ b/tests/GenericCounter_tb.wcfg
@@ -0,0 +1,56 @@
+<?xml version="1.0" encoding="UTF-8"?>
+<wave_config>
+   <wave_state>
+   </wave_state>
+   <db_ref_list>
+      <db_ref path="./isim.wdb" id="1" type="auto">
+         <top_modules>
+            <top_module name="genericcounter_tb" />
+            <top_module name="glbl" />
+            <top_module name="math_real" />
+            <top_module name="numeric_std" />
+            <top_module name="std_logic_1164" />
+         </top_modules>
+      </db_ref>
+   </db_ref_list>
+   <WVObjectSize size="9" />
+   <wvobject fp_name="/genericcounter_tb/clk" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">clk</obj_property>
+      <obj_property name="ObjectShortName">clk</obj_property>
+   </wvobject>
+   <wvobject fp_name="/genericcounter_tb/rst" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">rst</obj_property>
+      <obj_property name="ObjectShortName">rst</obj_property>
+   </wvobject>
+   <wvobject fp_name="/genericcounter_tb/ce" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">ce</obj_property>
+      <obj_property name="ObjectShortName">ce</obj_property>
+   </wvobject>
+   <wvobject fp_name="/genericcounter_tb/countenable" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">countenable</obj_property>
+      <obj_property name="ObjectShortName">countenable</obj_property>
+   </wvobject>
+   <wvobject fp_name="/genericcounter_tb/set" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">set</obj_property>
+      <obj_property name="ObjectShortName">set</obj_property>
+   </wvobject>
+   <wvobject fp_name="/genericcounter_tb/setvalue" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">setvalue[3:0]</obj_property>
+      <obj_property name="ObjectShortName">setvalue[3:0]</obj_property>
+      <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/genericcounter_tb/value" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">value[3:0]</obj_property>
+      <obj_property name="ObjectShortName">value[3:0]</obj_property>
+      <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/genericcounter_tb/lookaheadvalue" type="array" db_ref_id="1">
+      <obj_property name="ElementShortName">lookaheadvalue[3:0]</obj_property>
+      <obj_property name="ObjectShortName">lookaheadvalue[3:0]</obj_property>
+      <obj_property name="Radix">UNSIGNEDDECRADIX</obj_property>
+   </wvobject>
+   <wvobject fp_name="/genericcounter_tb/overunderflow" type="logic" db_ref_id="1">
+      <obj_property name="ElementShortName">overunderflow</obj_property>
+      <obj_property name="ObjectShortName">overunderflow</obj_property>
+   </wvobject>
+</wave_config>