110 lines
3.1 KiB
VHDL
110 lines
3.1 KiB
VHDL
----------------------------------------------------------------------------------
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-- @Name EPP
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-- @Version 0.2
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-- @Author Maximilian Passarello
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-- @E-Mail atom-dragon@gmx.net
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----------------------------------------------------------------------------------
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LIBRARY IEEE;
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USE IEEE.STD_LOGIC_1164.ALL;
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USE IEEE.NUMERIC_STD.ALL;
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ENTITY EPP IS
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GENERIC (RegisterQuant : INTEGER := 4);
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PORT (
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CLK : IN STD_LOGIC;
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CE : IN STD_LOGIC;
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RST : IN STD_LOGIC;
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EPPAddE : IN STD_LOGIC;
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EPPDataE : IN STD_LOGIC;
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EPPWE : IN STD_LOGIC;
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EPPD : INOUT STD_LOGIC_VECTOR(7 DOWNTO 0) := (OTHERS => 'Z');
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EPPWait : OUT STD_LOGIC;
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Dout : OUT STD_LOGIC_VECTOR((RegisterQuant * 8) - 1 DOWNTO 0);
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Din : IN STD_LOGIC_VECTOR((RegisterQuant * 8) - 1 DOWNTO 0));
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END EPP;
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ARCHITECTURE Behavioral OF EPP IS
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FUNCTION log2_ceil(N : INTEGER) RETURN INTEGER IS
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BEGIN
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IF (N <= 2) THEN
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RETURN 1;
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ELSE
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IF (N MOD 2 = 0) THEN
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RETURN 1 + log2_ceil(N/2);
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ELSE
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RETURN 1 + log2_ceil((N + 1)/2);
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END IF;
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END IF;
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END FUNCTION log2_ceil;
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TYPE RegisterType IS ARRAY(RegisterQuant - 1 DOWNTO 0)
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OF STD_LOGIC_VECTOR(7 DOWNTO 0);
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SIGNAL RegistersIn : RegisterType;
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SIGNAL RegistersOut : RegisterType;
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SIGNAL EPPDInternal : STD_LOGIC_VECTOR(7 DOWNTO 0);
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SIGNAL Adress : STD_LOGIC_VECTOR(log2_ceil(RegisterQuant) - 1 DOWNTO 0);
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BEGIN
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EPPWait <= '1' WHEN EPPDataE = '0' OR EPPAddE = '0' ELSE
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'0';
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EPPD <= EPPDInternal WHEN (EPPWE = '1') ELSE
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"ZZZZZZZZ";
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PROCESS (EPPAddE)
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BEGIN
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IF rising_edge(EPPAddE) THEN
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IF EPPWE = '0' THEN
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Adress <= EPPD(log2_ceil(RegisterQuant) - 1 DOWNTO 0);
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END IF;
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END IF;
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END PROCESS;
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-- process(EPPAddE)
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-- begin
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-- if falling_edge(EPPAddE) then
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-- if EPPWE = '1' then
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-- EPPDInternal(log2_ceil(RegisterQuant)-1 downto 0) <= Adress;
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-- end if;
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-- end if;
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-- end process;
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PROCESS (EPPDataE)
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BEGIN
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IF rising_edge(EPPDataE) THEN
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IF EPPWE = '0' THEN
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RegistersOut(to_integer(unsigned(Adress))) <= EPPD;
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END IF;
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END IF;
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END PROCESS;
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EPPDInternal <= RegistersIn(to_integer(unsigned(Adress)));
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PROCESS (CLK)
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BEGIN
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IF rising_edge(CLK) THEN
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IF RST = '1' THEN
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Dout <= (OTHERS => '0');
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ELSIF CE = '1' THEN
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FOR i IN 0 TO RegisterQuant - 1 LOOP
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Dout(((i + 1) * 8) - 1 DOWNTO ((i) * 8)) <= RegistersOut(i);
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END LOOP;
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END IF;
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END IF;
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END PROCESS;
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PROCESS (CLK)
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BEGIN
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IF rising_edge(CLK) THEN
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IF RST = '1' THEN
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NULL;
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ELSIF CE = '1' THEN
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FOR i IN 0 TO RegisterQuant - 1 LOOP
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RegistersIn(i) <= Din(((i + 1) * 8) - 1 DOWNTO ((i) * 8));
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END LOOP;
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END IF;
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END IF;
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END PROCESS;
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END Behavioral; |