From b6adb0b615f6851c323ecbbf393fb0f8f123f52f Mon Sep 17 00:00:00 2001 From: Max P Date: Sun, 27 Apr 2025 19:41:13 +0000 Subject: [PATCH] Migrates project to devcontainer setup and YAML-based configuration Introduces a devcontainer configuration for consistent development environments. Replaces `.gitmodules` and `project.cfg` with a more flexible `project.yml` format. Renames and reorganizes source files under a unified `src` directory structure. Updates `.gitignore` to reflect new build and configuration paths. Improves project maintainability and simplifies dependency management. --- .devcontainer/devcontainer.json | 30 ++++ .gitignore | 8 +- .gitmodules | 3 - build | 1 - project.cfg | 89 ----------- project.yml | 268 ++++++++++++++++++++++++++++++++ {code => src}/DEPP.vhd | 0 {code => src}/Nexys2Test.ucf | 0 {code => src}/Nexys2Test.vhd | 0 9 files changed, 304 insertions(+), 95 deletions(-) create mode 100644 .devcontainer/devcontainer.json delete mode 100644 .gitmodules delete mode 160000 build delete mode 100644 project.cfg create mode 100644 project.yml rename {code => src}/DEPP.vhd (100%) rename {code => src}/Nexys2Test.ucf (100%) rename {code => src}/Nexys2Test.vhd (100%) diff --git a/.devcontainer/devcontainer.json b/.devcontainer/devcontainer.json new file mode 100644 index 0000000..7f86103 --- /dev/null +++ b/.devcontainer/devcontainer.json @@ -0,0 +1,30 @@ +{ + "name": "Xilinx ISE 14.7", + "image": "xilinx-ise:14.7", + "runArgs": [ + "--privileged", + "--cap-add=SYS_ADMIN", + "--shm-size=2g", + "-v", + "/run/user/1000/gnupg/S.gpg-agent:/run/user/1000/gnupg/S.gpg-agent" + ], + "customizations": { + "vscode": { + "extensions": [ + "/home/xilinx/vsxirepo/vhdl-by-hgb.vsix", + "eamodio.gitlens" + ], + "settings": { + "terminal.integrated.defaultProfile.linux": "bash" + } + } + }, + "remoteUser": "xilinx", + "workspaceMount": "source=${localWorkspaceFolder},target=/workspaces/${localWorkspaceFolderBasename},type=bind", + "workspaceFolder": "/workspaces/${localWorkspaceFolderBasename}", + "features": {}, + "forwardPorts": [ + 10000 + ], + "postStartCommand": "git config --global user.signingkey 87C8A5DD5C14DF55DBE1DB4199AC216D447E61C0 && git config --global gpg.format openpgp && git config --global commit.gpgsign true && git config --global tag.forceSignAnnotated true && sudo apt update && sudo apt upgrade -y" +} \ No newline at end of file diff --git a/.gitignore b/.gitignore index 21b33ec..7394369 100644 --- a/.gitignore +++ b/.gitignore @@ -1,2 +1,6 @@ -build/working/ -copy.sh +.hdlbuild_deps/ +.working/ +reports/ +output/ +.locale/ +vhdl_ls.toml \ No newline at end of file diff --git a/.gitmodules b/.gitmodules deleted file mode 100644 index cfb31af..0000000 --- a/.gitmodules +++ /dev/null @@ -1,3 +0,0 @@ -[submodule "build"] - path = build - url = git@github.com:PxaMMaxP/Xilinx-ISE-Makefile.git diff --git a/build b/build deleted file mode 160000 index a8ed470..0000000 --- a/build +++ /dev/null @@ -1 +0,0 @@ -Subproject commit a8ed470e7de04ce923360ec480f3087795f136d6 diff --git a/project.cfg b/project.cfg deleted file mode 100644 index 5e54670..0000000 --- a/project.cfg +++ /dev/null @@ -1,89 +0,0 @@ -## Main settings.. ## - -# Project name -# @remark The name of the project is used as default name for the top module and the ucf file -PROJECT = DEPP - -# Target device -# @example xc3s1200e-4-fg320 | xc5vlx50t-1-ff1136 -TARGET_PART = xc3s1200e-4-fg320 - -# Path to the Xilinx ISE installation -XILINX = /opt/Xilinx/14.7/ISE_DS/ISE - -# Optional the name of the top module (default is the project name) -TOPLEVEL = Nexys2Test - -# Optional the name of the ucf file (default is the project name) -CONSTRAINTS = code/Nexys2Test.ucf - -## ## ## ## ## ## ## ## -# --------------------- - -## Source files settings.. ## -# The source files to be compiled -# @example `VSOURCE += src/main.v` (add a single Verilog file per line) -# @example `VHDSOURCE += src/main.vhd` (add a single VHDL file per line) - -VHDSOURCE += code/Nexys2Test.vhd -VHDSOURCE += code/DEPP.vhd - -## ## ## ## ## ## ## ## -# --------------------- - -## ISE executable settings.. ## - -# General command line options to be passed to all ISE executables (default is `-intstyle xflow`) -# COMMON_OPTS = -# Options for the XST synthesizer -# XST_OPTS = - -# Options for the NGDBuild tool -# NGDBUILD_OPTS = - -# Options for the MAP tool -# @example -mt 2 (multi-threading with 2 threads) -# MAP_OPTS = - -# Options for the PAR tool -# @example -mt 2 (multi-threading with 2 threads) -# PAR_OPTS = - -# Options for the BitGen tool -# @example -g Compress (compress bitstream) -# @example -g StartupClk:Cclk (specify the startup clock to onboard clock) -# @example -g StartupClk:JtagClk (specify the startup clock to JTAG clock) -# BITGEN_OPTS = - -# Options for the Trace tool -# TRACE_OPTS = - -# Options for the Fuse tool -# FUSE_OPTS = - -## ## ## ## ## ## ## ## -# --------------------- - -## Programmer settings.. ## - -# The programmer to use -# @example impact | digilent | xc3sprog -# @remark impact is the default Xilinx programmer and you must create a impact.cmd file in the root directory.. -PROGRAMMER = digilent - -## Digilent JTAG cable settings - -# @remark Use the `djtgcfg enum` command to list all available devices -DJTG_DEVICE = DOnbUsb - -# The index of the JTAG device for the `prog` target -DJTG_INDEX = 0 - -# The index of the flash device for the `flash` target -DJTG_FLASH_INDEX = 1 - -# Pre-programmer command -PROGRAMMER_PRE = yes Y | sudo - -## ## ## ## ## ## ## ## -# --------------------- \ No newline at end of file diff --git a/project.yml b/project.yml new file mode 100644 index 0000000..a302a38 --- /dev/null +++ b/project.yml @@ -0,0 +1,268 @@ +name: DEPP +topmodule: Nexys2Test +target_device: xc3s1200e-4-fg320 +xilinx_path: /opt/Xilinx/14.7/ISE_DS/ISE + +constraints: src/Nexys2Test.ucf + +sources: + vhdl: + - path: src/*.vhd + library: work + +testbenches: + vhdl: + - path: tests/*.vhd + library: work + +dependencies: + # - git: "https://git.0xmax42.io/maxp/Asynchronous-FIFO-AXI-Handshake.git" + # rev: "hdlbuild" + +build: + build_dir: working + report_dir: reports + copy_target_dir: output + +# Tool Optionen +tool_options: + common: + - "-intstyle" + - "xflow" + + ngdbuild: [] + + map: + - "-detail" + - "-timing" + - "-ol" + - "high" + + par: [] + + bitgen: + - "-g" + - "StartupClk:JtagClk" + + trace: + - "-v" + - "3" + - "-n" + - "3" + + fuse: + - "-incremental" + + isim: + - "-gui" + + xst: + # Optimization goal: prioritize speed or area. + # Values: Speed | Area + - "-opt_mode Speed" + + # Optimization level: more aggressive optimizations at level 2. + # Values: 1 | 2 + - "-opt_level 2" + + # Use the new XST parser (recommended for modern designs). + # Values: yes | no + - "-use_new_parser yes" + + # Preserve design hierarchy or allow flattening for optimization. + # Values: Yes | No | Soft + - "-keep_hierarchy No" + + # Determines how hierarchy is preserved in the netlist. + # Values: As_Optimized | Rebuilt + - "-netlist_hierarchy As_Optimized" + + # Global optimization strategy for nets. + # Values: AllClockNets | Offset_In_Before | Offset_Out_After | Inpad_To_Outpad | Max_Delay + - "-glob_opt AllClockNets" + + ## Misc ## + + # Enable reading of IP cores. + # Values: YES | NO + - "-read_cores YES" + + # Do not write timing constraints into synthesis report. + # Values: YES | NO + - "-write_timing_constraints NO" + + # Analyze paths across different clock domains. + # Values: YES | NO + - "-cross_clock_analysis NO" + + # Character used to separate hierarchy levels in instance names. + # Default: / + - "-hierarchy_separator /" + + # Delimiters used for bus signals. + # Values: <> | [] | () | {} + - "-bus_delimiter <>" + + # Maintain original case of identifiers. + # Values: Maintain | Upper | Lower + - "-case Maintain" + + # Target maximum utilization ratio for slices. + # Values: 1–100 + - "-slice_utilization_ratio 100" + + # Target maximum utilization ratio for BRAMs. + # Values: 1–100 + - "-bram_utilization_ratio 100" + + # Use Verilog 2001 syntax features. + # Values: YES | NO + - "-verilog2001 YES" + + #### HDL Options #### + + ## FSM ## + + # Extract FSMs (Finite State Machines) from HDL code. + # Values: YES | NO + - "-fsm_extract YES" + + # Encoding strategy for FSMs. + # Values: Auto | Gray | One-Hot | Johnson | Compact | Sequential | Speed1 | User + - "-fsm_encoding Auto" + + # Add safe logic for undefined FSM states. + # Values: Yes | No + - "-safe_implementation No" + + # Structure used to implement FSMs. + # Values: LUT | BRAM + - "-fsm_style LUT" + + ## RAM/ROM ## + + # Extract RAM inference from HDL. + # Values: Yes | No + - "-ram_extract Yes" + + # Style used to implement RAM. + # Values: Auto | Block | Distributed + - "-ram_style Auto" + + # Extract ROM inference from HDL. + # Values: Yes | No + - "-rom_extract Yes" + + # Style used for implementing ROM. + # Values: Auto | Distributed | Block + - "-rom_style Auto" + + # Enable or disable automatic BRAM packing. + # Values: YES | NO + - "-auto_bram_packing NO" + + ## MUX/Decoder/Shift Register ## + + # Extract multiplexers where possible. + # Values: Yes | No | Force + - "-mux_extract Yes" + + # Style used for implementing MUX logic. + # Values: Auto | MUXCY | MUXF + - "-mux_style Auto" + + # Extract decoder logic from behavioral code. + # Values: YES | NO + - "-decoder_extract YES" + + # Extract and optimize priority encoder structures. + # Values: Yes | No | Force + - "-priority_extract Yes" + + # Extract shift register logic. + # Values: YES | NO + - "-shreg_extract YES" + + # Extract simple shift operations into dedicated hardware. + # Values: YES | NO + - "-shift_extract YES" + + ## Multiplier ## + + # Style for implementing multipliers. + # Values: Auto | LUT | Pipe_LUT | Pipe_Block | Block + - "-mult_style Auto" + + ## Misc ## + + # Collapse XOR trees where beneficial. + # Values: YES | NO + - "-xor_collapse YES" + + # Share resources like adders or multipliers between logic blocks. + # Values: YES | NO | Force + - "-resource_sharing YES" + + # Convert asynchronous resets to synchronous where possible. + # Values: YES | NO + - "-async_to_sync NO" + + #### Xilinx Specific Options #### + + ## Optimization ## + + # Enable removal of logically equivalent registers. + # Values: YES | NO + - "-equivalent_register_removal YES" + + # Duplicate registers to reduce fanout or improve timing. + # Values: YES | NO + - "-register_duplication YES" + + # Move registers across logic to balance timing. + # Values: Yes | No | Forward | Backward + - "-register_balancing No" + + # Use clock enable signals where possible. + # Values: Auto | Yes | No + - "-use_clock_enable Yes" + + # Use synchronous set (preset) signals when available. + # Values: Auto | Yes | No + - "-use_sync_set Yes" + + # Use synchronous reset signals where possible. + # Values: Auto | Yes | No + - "-use_sync_reset Yes" + + ## I/O ## + + # Insert IO buffers for top-level ports. + # Values: YES | NO + - "-iobuf YES" + + # Placement strategy for IOB registers (Auto = let tools decide). + # Values: Auto | YES | NO + - "-iob Auto" + + ## Misc ## + + # Maximum allowed fanout for a net. + # Values: integer (e.g., 500) + - "-max_fanout 500" + + # Maximum number of BUFGs (global buffers) to use. + # Values: 0–32 (device-dependent) + - "-bufg 24" + + # Enable logic packing into slices. + # Values: YES | NO + - "-slice_packing YES" + + # Try to reduce the number of primitive instances used. + # Values: YES | NO + - "-optimize_primitives NO" + + # Margin in percent beyond the target slice utilization. + # Values: 0–100 + - "-slice_utilization_ratio_maxmargin 5" \ No newline at end of file diff --git a/code/DEPP.vhd b/src/DEPP.vhd similarity index 100% rename from code/DEPP.vhd rename to src/DEPP.vhd diff --git a/code/Nexys2Test.ucf b/src/Nexys2Test.ucf similarity index 100% rename from code/Nexys2Test.ucf rename to src/Nexys2Test.ucf diff --git a/code/Nexys2Test.vhd b/src/Nexys2Test.vhd similarity index 100% rename from code/Nexys2Test.vhd rename to src/Nexys2Test.vhd