dev (#1)
* Enhanced edge detection in DEPP Updated the DEPP VHDL component with clearer comment annotations and modified edge detection logic for address and data enable signals. Additionally, refined the main state machine by explicitly adding states for edge waiting periods and defining behaviors for each state, specifically regarding the handling of output FIFO signals and cycle initiation. Updated the edge detection mechanism within the address and data processing workflows, improving cycle handling for idle, address, and data states to better signal the transitions and manage the bus as well as the request and write enable signals. * Implement FIFO compatible interface and update waveforms Enhanced DEPP documentation and diagrams to reflect a transition to FIFO compatible interfaces for data traffic efficiency. Updated waveforms depict the revised cycle timings for data/address commands and address acknowledgment, ensuring clarity on the implemented protocol changes. * Refine DEPP VHDL port naming for clarity Updated the DEPP VHDL entity's port naming convention to enhance readability and consistency across data and address lines. Introduced clear "Fifo" and "AddressOut" prefixes as per FIFO compatible interfaces, replacing generic data and address signal names. This renaming also strengthens the association between ports and their respective data flow. Additional changes include: - Replaced 'DataAviable' with a negated 'DataInFifo_EmptyFlag' for immediate data availability check. - Streamlined write enable signals alignment with the new naming convention. - Redesigned read-enable logic to minimize latency in 'RequestActive' mode by directly relaying the 'DataInFifo_DataAviable' status. - Simplified and restructured bus wait management states to reflect the updated port names and signal handling improvements. - Removed obsolete comments and updated documentation to accurately reflect the current interface functionality and structure. * Enhanced DEPP module docs and waveform references - Updated the DEPP module documentation to improve clarity and readability. - Refactoring included renaming of waveform files for consistency and eliminating unnecessary whitespace. - Revised virtual bus interface descriptions for better accuracy and cleared up the ambiguity in port names and their corresponding descriptions. - Streamlined the ports and signals tables to enhance document structure and coherence. - Modified the state machine SVG file for an up-to-date representation of the module design. - Integrated additional waveform diagrams to detail the EPP (Enhanced Parallel Port) bus cycles within the documentation. * Optimized EPP state machine timing Refactored the EPP (Enhanced Parallel Port) VHDL state machine to streamline the signal handling for different operating states. This optimization includes removing redundant assignments to the `DEPP_Wait` signal in intermediary states and ensuring it is only held high for a minimum of one cycle where necessary. These modifications enhance the clarity of state transitions and may improve the system's timing performance, particularly for the start of read, write, and address cycles. Additionally, the documentation is updated to include measured data rates, aiding in setting performance expectations. * Enhanced UCF readability and added LA constraints Reformatted the pin constraints section in Nexys2Test.ucf to improve readability, adding descriptive comments for RST, DataOutFullFlag, and RequestFullFlag signals. Removed unnecessary net constraints related to DEPP interface signals. Extended the UCF to include configuration for the Logic Analyzer (LA), specifying appropriate locations and providing comments linking net names to their corresponding physical connectors. * Refactor signal handling and add Logic Analyzer output Updated the Nexys2Test VHDL entity to streamline signal handling and add support for a Logic Analyzer interface. Removed commented-out attributes for virtual bus and related signals, which simplifies the interface section. Introduced new outputs for the Logic Analyzer to monitor various signals such as address, data enable, write enable, and wait signals, which improves debug and testing capabilities. In the architecture, redundant process handling DEPP_Wait has been removed to reduce complexity, and DEPP_Bus is now directly assigned. Updated the main process to simplify LED assignments and fixed an incorrect value for DataInFifo_EmptyFlag, enhancing signal accuracy and conforming to expected logic levels. These changes contribute to a more maintainable and understandable codebase. * Update EPP documentation with data rate and refreshed diagrams - Added the measured data transfer rate to the DEPP documentation. - Replaced EPP bus waveform diagrams with updated versions. - Resized and restructured the DEPP FSM SVG for better legibility, including adjustments to cluster dimensions, node positions, edges, and transitions. - Renamed waveform SVG files for a consistent naming convention. * Added logic analyzer capture visuals for documentation * Added MIT License and enhanced README for DEPP module Implemented an MIT License file and updated the README to provide comprehensive documentation for the VHDL Module designed for the Digilent Asynchronous Parallel Port Interface. The README now includes an overview of the module's purpose, features such as the measured data rate, visual diagrams for bus cycles, a detailed port definition table, module dependencies, contribution guidelines, licensing information, and acknowledgments, improving clarity and usability for end-users and contributors. Co-authored-by: Max P <Mail@MPassarello.de> Co-committed-by: Max P <Mail@MPassarello.de>
This commit is contained in:
1
.gitignore
vendored
1
.gitignore
vendored
@@ -1 +1,2 @@
|
||||
build/
|
||||
copy.sh
|
||||
|
||||
21
LICENSE
Normal file
21
LICENSE
Normal file
@@ -0,0 +1,21 @@
|
||||
MIT License
|
||||
|
||||
Copyright (c) 2024 Maximilian Passarello
|
||||
|
||||
Permission is hereby granted, free of charge, to any person obtaining a copy
|
||||
of this software and associated documentation files (the "Software"), to deal
|
||||
in the Software without restriction, including without limitation the rights
|
||||
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
|
||||
copies of the Software, and to permit persons to whom the Software is
|
||||
furnished to do so, subject to the following conditions:
|
||||
|
||||
The above copyright notice and this permission notice shall be included in all
|
||||
copies or substantial portions of the Software.
|
||||
|
||||
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
|
||||
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
|
||||
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
|
||||
SOFTWARE.
|
||||
60
Makefile
60
Makefile
@@ -6,8 +6,18 @@
|
||||
## worldwide. This software is distributed without any warranty.
|
||||
###########################################################################
|
||||
|
||||
include project.cfg
|
||||
###########################################################################
|
||||
# Version
|
||||
###########################################################################
|
||||
|
||||
Makefile_Version := 1.0.0
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||||
$(info ISE Makefile Version: $(Makefile_Version))
|
||||
|
||||
###########################################################################
|
||||
# Include project configuration
|
||||
###########################################################################
|
||||
|
||||
include project.cfg
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||||
|
||||
###########################################################################
|
||||
# Default values
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||||
@@ -32,19 +42,21 @@ BITFILE ?= build/$(PROJECT).bit
|
||||
COMMON_OPTS ?= -intstyle xflow
|
||||
XST_OPTS ?=
|
||||
NGDBUILD_OPTS ?=
|
||||
MAP_OPTS ?=
|
||||
MAP_OPTS ?= -detail
|
||||
PAR_OPTS ?=
|
||||
BITGEN_OPTS ?=
|
||||
TRACE_OPTS ?=
|
||||
TRACE_OPTS ?= -v 3 -n 3
|
||||
FUSE_OPTS ?= -incremental
|
||||
|
||||
PROGRAMMER ?= none
|
||||
PROGRAMMER_PRE ?=
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||||
|
||||
IMPACT_OPTS ?= -batch impact.cmd
|
||||
|
||||
DJTG_EXE ?= djtgcfg
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||||
DJTG_DEVICE ?= DJTG_DEVICE-NOT-SET
|
||||
DJTG_INDEX ?= 0
|
||||
DJTG_FLASH_INDEX ?= 1
|
||||
|
||||
XC3SPROG_EXE ?= xc3sprog
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||||
XC3SPROG_CABLE ?= none
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||||
@@ -76,6 +88,28 @@ RUN = @echo "\n\e[1;33m============ $(1) ============\e[m\n"; \
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||||
# isim executables don't work without this
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export XILINX
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||||
|
||||
# Initialize the libs and paths variables for VHDL and Verilog sources
|
||||
VHD_PATHS ?=
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VHD_LIBS ?=
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||||
V_PATHS ?=
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V_LIBS ?=
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||||
|
||||
# Define a function to process source files
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||||
define process_sources
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||||
$(foreach src,$(1),\
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||||
$(eval lib_and_path=$(subst :, ,$(src))) \
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||||
$(eval libname=$(word 1,$(lib_and_path))) \
|
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$(eval filepath=$(word 2,$(lib_and_path))) \
|
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$(if $(filepath),,$(eval filepath=$(libname)) $(eval libname=work)) \
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||||
$(eval $(2) += $(libname)) \
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||||
$(eval $(3) += $(filepath)) \
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||||
)
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||||
endef
|
||||
|
||||
# Run the function for VHDL sources
|
||||
$(eval $(call process_sources,$(VHDSOURCE),VHD_LIBS,VHD_PATHS))
|
||||
# Run the function for Verilog sources
|
||||
$(eval $(call process_sources,$(VSOURCE),V_LIBS,V_PATHS))
|
||||
|
||||
###########################################################################
|
||||
# Default build
|
||||
@@ -90,8 +124,9 @@ build/$(PROJECT).prj: project.cfg
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||||
@echo "Updating $@"
|
||||
@mkdir -p build
|
||||
@rm -f $@
|
||||
@$(foreach file,$(VSOURCE),echo "verilog work \"../$(file)\"" >> $@;)
|
||||
@$(foreach file,$(VHDSOURCE),echo "vhdl work \"../$(file)\"" >> $@;)
|
||||
@$(foreach idx,$(shell seq 1 $(words $(V_PATHS))),echo "verilog $(word $(idx),$(V_LIBS)) \"../$(word $(idx),$(V_PATHS))\"" >> $@;)
|
||||
@$(foreach idx,$(shell seq 1 $(words $(VHD_PATHS))),echo "vhdl $(word $(idx),$(VHD_LIBS)) \"../$(word $(idx),$(VHD_PATHS))\"" >> $@;)
|
||||
|
||||
|
||||
build/$(PROJECT)_sim.prj: build/$(PROJECT).prj
|
||||
@cp build/$(PROJECT).prj $@
|
||||
@@ -113,7 +148,7 @@ build/$(PROJECT).scr: project.cfg
|
||||
"-p $(TARGET_PART)" \
|
||||
> build/$(PROJECT).scr
|
||||
|
||||
$(BITFILE): project.cfg $(VSOURCE) $(CONSTRAINTS) build/$(PROJECT).prj build/$(PROJECT).scr
|
||||
$(BITFILE): project.cfg $(V_PATHS) $(VHD_PATHS) $(CONSTRAINTS) build/$(PROJECT).prj build/$(PROJECT).scr
|
||||
@mkdir -p build
|
||||
$(call RUN,xst) $(COMMON_OPTS) \
|
||||
-ifn $(PROJECT).scr
|
||||
@@ -153,7 +188,7 @@ trace: project.cfg $(BITFILE)
|
||||
|
||||
test: $(TEST_EXES)
|
||||
|
||||
build/isim_%$(EXE): build/$(PROJECT)_sim.prj $(VSOURCE) $(VHDSOURCE) $(VTEST) $(VHDTEST)
|
||||
build/isim_%$(EXE): $(V_PATHS) $(VHD_PATHS) build/$(PROJECT)_sim.prj $(VTEST) $(VHDTEST)
|
||||
$(call RUN,fuse) $(COMMON_OPTS) $(FUSE_OPTS) \
|
||||
-prj $(PROJECT)_sim.prj \
|
||||
-o isim_$*$(EXE) \
|
||||
@@ -176,17 +211,17 @@ isimgui: build/isim_$(TB)$(EXE)
|
||||
|
||||
ifeq ($(PROGRAMMER), impact)
|
||||
prog: $(BITFILE)
|
||||
sudo $(XILINX)/bin/$(XILINX_PLATFORM)/impact $(IMPACT_OPTS)
|
||||
$(PROGRAMMER_PRE) $(XILINX)/bin/$(XILINX_PLATFORM)/impact $(IMPACT_OPTS)
|
||||
endif
|
||||
|
||||
ifeq ($(PROGRAMMER), digilent)
|
||||
prog: $(BITFILE)
|
||||
yes Y | sudo $(DJTG_EXE) prog -d $(DJTG_DEVICE) -i $(DJTG_INDEX) -f $(BITFILE)
|
||||
$(PROGRAMMER_PRE) $(DJTG_EXE) prog -d $(DJTG_DEVICE) -i $(DJTG_INDEX) -f $(BITFILE)
|
||||
endif
|
||||
|
||||
ifeq ($(PROGRAMMER), xc3sprog)
|
||||
prog: $(BITFILE)
|
||||
sudo $(XC3SPROG_EXE) -c $(XC3SPROG_CABLE) $(XC3SPROG_OPTS) $(BITFILE)
|
||||
$(PROGRAMMER_PRE) $(XC3SPROG_EXE) -c $(XC3SPROG_CABLE) $(XC3SPROG_OPTS) $(BITFILE)
|
||||
endif
|
||||
|
||||
ifeq ($(PROGRAMMER), none)
|
||||
@@ -200,10 +235,7 @@ endif
|
||||
|
||||
ifeq ($(PROGRAMMER), digilent)
|
||||
flash: $(BITFILE)
|
||||
yes Y | sudo $(DJTG_EXE) prog -d $(DJTG_DEVICE) -i $(DJTG_FLASH_INDEX) -f $(BITFILE)
|
||||
$(PROGRAMMER_PRE) $(DJTG_EXE) prog -d $(DJTG_DEVICE) -i $(DJTG_FLASH_INDEX) -f $(BITFILE)
|
||||
endif
|
||||
|
||||
|
||||
###########################################################################
|
||||
|
||||
# vim: set filetype=make: #
|
||||
|
||||
59
README.md
59
README.md
@@ -1,45 +1,52 @@
|
||||
# English
|
||||
# VHDL Module for the Digilent Asynchronous Parallel Port Interface (DEPP)
|
||||
|
||||
## VHDL Project Template Using Xilinx Build Tools with Makefile
|
||||
## Overview
|
||||
|
||||
Welcome to the VHDL Project Template repository. This project is designed to streamline your FPGA development process using the Xilinx ISE Build Tools, integrated with a convenient Makefile approach for building and synthesizing your VHDL designs.
|
||||
The `DEPP.vhd` module is designed as an Enhanced Parallel Port (EPP) interface for use with Digilent FPGA boards. It facilitates communication between a host computer and the FPGA via the Digilent Adept software, supporting operations such as address write, data write, and data read cycles.
|
||||
|
||||
### Using the Makefile
|
||||
## Features
|
||||
|
||||
To use the Makefile for building your VHDL projects, ensure you have the Xilinx Build Tools installed on your system. The Makefile is specifically configured to work with these tools to automate the build process.
|
||||
- Designed for integration with Digilent FPGA boards.
|
||||
- Supports data transfers with Digilent Adept software.
|
||||
- Measured data rate of approximately 4.68 kByte/s.
|
||||
|
||||
For detailed instructions on how to use the Makefile, please refer to the following URL: [Xilinx ISE Makefile](https://github.com/PxaMMaxP/Xilinx-ISE-Makefile). This page contains comprehensive guidance on setup and usage to get you started quickly.
|
||||
## Bus Cycles Visualized
|
||||
|
||||
### Directory Structure
|
||||
- EPP Address Write Cycle
|
||||
|
||||
|
||||
The project is organized into various subdirectories, each serving a specific role in the development process. For an explanation of the directory structure and the contents of each subdirectory, please refer to the `README.md` files located within the subdirectories. These documents provide valuable insights into how the project is organized and how to navigate the files and folders efficiently.
|
||||
- EPP Data Write Cycle
|
||||
|
||||
|
||||
### Getting Started
|
||||
- EPP Data Read Cycle
|
||||
|
||||
|
||||
To begin using this VHDL Project Template, clone the repository to your local machine and follow the instructions provided in the subdirectory `README.md` files to understand the project layout. Then, head over to the URL mentioned above for details on using the Makefile with the Xilinx Build Tools.
|
||||
## Port Definitions
|
||||
|
||||
Thank you for choosing this VHDL Project Template. We hope it accelerates your development process and helps you achieve your project goals efficiently.
|
||||
| Port Name | Direction | Type | Description |
|
||||
| ---------------- | --------- | ----------- | -------------------------------------------------- |
|
||||
| CLK | in | std_logic | Clock signal. Rising edge triggered. |
|
||||
| CE | in | std_logic | Chip enable. `1` = enabled, `0` = disabled. |
|
||||
| RST | in | std_logic | Reset signal. `1` = reset, `0` = normal operation. |
|
||||
| EPP-Interface | out | Virtual bus | EPP Interface for address and data operations. |
|
||||
| FIFO-Data-Out | out | Virtual bus | FIFO compatible data and address output interface. |
|
||||
| FIFO-Data-In | in | Virtual bus | FIFO compatible data input interface. |
|
||||
| FIFO-Address-Out | out | Virtual bus | FIFO compatible request address output interface. |
|
||||
|
||||
---
|
||||
Detailed information on virtual bus port configurations can be found within the [module's documentation](docs/DEPP/DEPP.md).
|
||||
|
||||
# Deutsch
|
||||
## Dependencies
|
||||
|
||||
## VHDL-Projektvorlage unter Verwendung von Xilinx Build Tools mit Makefile
|
||||
The module depends on standard logic and numeric libraries available in VHDL. Ensure you have the latest version of the Digilent Adept software for proper interfacing with the module.
|
||||
|
||||
Willkommen im Repository der VHDL-Projektvorlage. Dieses Projekt wurde entwickelt, um Ihren FPGA-Entwicklungsprozess mit den Xilinx ISE Build Tools zu vereinfachen, integriert mit einem praktischen Makefile-Ansatz zum Bauen und Synthetisieren Ihrer VHDL-Designs.
|
||||
## Contributing
|
||||
|
||||
### Verwendung des Makefiles
|
||||
Contributions to improve the module or extend its capabilities are welcome. Please adhere to the existing coding standards and provide documentation for any changes made.
|
||||
|
||||
Um das Makefile für den Bau Ihrer VHDL-Projekte zu verwenden, stellen Sie sicher, dass die Xilinx Build Tools auf Ihrem System installiert sind. Das Makefile ist speziell so konfiguriert, dass es mit diesen Tools arbeitet, um den Bauprozess zu automatisieren.
|
||||
## License
|
||||
|
||||
Für detaillierte Anweisungen zur Verwendung des Makefiles besuchen Sie bitte die folgende URL: [Xilinx ISE Makefile](https://github.com/PxaMMaxP/Xilinx-ISE-Makefile). Diese Seite enthält umfassende Anleitungen zur Einrichtung und Verwendung, damit Sie schnell starten können.
|
||||
This module is open source and is distributed under the MIT license. Please see the [LICENSE](LICENSE) file for full details.
|
||||
|
||||
### Verzeichnisstruktur
|
||||
## Acknowledgments
|
||||
|
||||
Das Projekt ist in verschiedene Unterverzeichnisse organisiert, von denen jedes eine spezifische Rolle im Entwicklungsprozess spielt. Für eine Erklärung der Verzeichnisstruktur und des Inhalts jedes Unterverzeichnisses beachten Sie bitte die `README.md`-Dateien, die sich in den Unterverzeichnissen befinden. Diese Dokumente bieten wertvolle Einblicke, wie das Projekt organisiert ist und wie Sie effizient durch die Dateien und Ordner navigieren.
|
||||
|
||||
### Erste Schritte
|
||||
|
||||
Um mit dieser VHDL-Projektvorlage zu beginnen, klonen Sie das Repository auf Ihre lokale Maschine und folgen Sie den Anweisungen in den `README.md`-Dateien der Unterverzeichnisse, um das Layout des Projekts zu verstehen. Anschließend besuchen Sie die oben genannte URL für Details zur Verwendung des Makefiles mit den Xilinx Build Tools.
|
||||
|
||||
Vielen Dank, dass Sie sich für diese VHDL-Projektvorlage entschieden haben. Wir hoffen, dass sie Ihren Entwicklungsprozess beschleunigt und Ihnen hilft, Ihre Projektziele effizient zu erreichen.
|
||||
Special thanks to the Digilent team for providing a reference manual in which the diagrams and the description in the text are contradictory ;-)
|
||||
|
||||
@@ -1,36 +0,0 @@
|
||||
NET CLK LOC = B8;
|
||||
NET CLK TNM_NET = CLOCK;
|
||||
TIMESPEC TS_CLOCK = PERIOD CLOCK 50 MHz HIGH 50 %;
|
||||
|
||||
NET "Dout<0>" LOC = "J14"; # Bank = 1, Pin name = IO_L14N_1/A3/RHCLK7, Type = RHCLK/DUAL, Sch name = JD10/LD0
|
||||
NET "Dout<1>" LOC = "J15"; # Bank = 1, Pin name = IO_L14P_1/A4/RHCLK6, Type = RHCLK/DUAL, Sch name = JD9/LD1
|
||||
NET "Dout<2>" LOC = "K15"; # Bank = 1, Pin name = IO_L12P_1/A8/RHCLK2, Type = RHCLK/DUAL, Sch name = JD8/LD2
|
||||
NET "Dout<3>" LOC = "K14"; # Bank = 1, Pin name = IO_L12N_1/A7/RHCLK3/TRDY1, Type = RHCLK/DUAL, Sch name = JD7/LD3
|
||||
NET "Dout<4>" LOC = "E16"; # Bank = 1, Pin name = N.C., Type = N.C., Sch name = LD4? other than s3e500
|
||||
NET "Dout<5>" LOC = "P16"; # Bank = 1, Pin name = N.C., Type = N.C., Sch name = LD5? other than s3e500
|
||||
NET "Dout<6>" LOC = "E4"; # Bank = 3, Pin name = N.C., Type = N.C., Sch name = LD6? other than s3e500
|
||||
NET "Dout<7>" LOC = "P4"; # Bank = 3, Pin name = N.C., Type = N.C., Sch name = LD7? other than s3e500
|
||||
|
||||
NET "Din<0>" LOC = "G18"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW0
|
||||
NET "Din<1>" LOC = "H18"; # Bank = 1, Pin name = IP/VREF_1, Type = VREF, Sch name = SW1
|
||||
NET "Din<2>" LOC = "K18"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW2
|
||||
NET "Din<3>" LOC = "K17"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW3
|
||||
NET "Din<4>" LOC = "L14"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW4
|
||||
NET "Din<5>" LOC = "L13"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW5
|
||||
NET "Din<6>" LOC = "N17"; # Bank = 1, Pin name = IP, Type = INPUT, Sch name = SW6
|
||||
NET "Din<7>" LOC = "R17"; # Bank = 1, Pin name = IP, Type = INPUT,
|
||||
|
||||
|
||||
NET "DEPP_AddressEnable" LOC = "V14" | CLOCK_DEDICATED_ROUTE = FALSE;
|
||||
NET "DEPP_DataEnable" LOC = "U14" | CLOCK_DEDICATED_ROUTE = FALSE;
|
||||
NET "DEPP_WriteEnable" LOC = "V16";
|
||||
NET "DEPP_Wait" LOC = "N9";
|
||||
|
||||
NET "DEPP_Bus<0>" LOC = "R14";
|
||||
NET "DEPP_Bus<1>" LOC = "R13";
|
||||
NET "DEPP_Bus<2>" LOC = "P13";
|
||||
NET "DEPP_Bus<3>" LOC = "T12";
|
||||
NET "DEPP_Bus<4>" LOC = "N11";
|
||||
NET "DEPP_Bus<5>" LOC = "R11";
|
||||
NET "DEPP_Bus<6>" LOC = "P10";
|
||||
NET "DEPP_Bus<7>" LOC = "R10";
|
||||
354
code/DEPP.vhd
354
code/DEPP.vhd
@@ -1,13 +1,18 @@
|
||||
----------------------------------------------------------------------------------
|
||||
-- @name Digilent EPP Interface
|
||||
-- @version 0.3.0
|
||||
-- @version 0.3.1
|
||||
-- @author Maximilian Passarello (mpassarello.de)
|
||||
--@ An EPP interface for Digilent FPGA boards
|
||||
--@ This interface is designed to be used with the Digilent EPP interface
|
||||
--@ and the Digilent Adept software.
|
||||
--@
|
||||
--@ **Measured data rate ≈ 4.68 kByte/s**
|
||||
--@
|
||||
--@ Below are diagrams of the EPP bus:
|
||||
-- @history
|
||||
-- - 0.2.0 (2010.05.30) Initial version
|
||||
-- - 0.3.0 (2024.03.06) Refactored and commented
|
||||
-- - 0.3.1 (2024.03.07) TODO
|
||||
----------------------------------------------------------------------------------
|
||||
-- Timing Diagram's
|
||||
-- EPP Address Write
|
||||
@@ -29,16 +34,52 @@
|
||||
--@ },
|
||||
--@ "edge": ["A+B min. 80 ns", "C+D min. 40ns", "E+F 0 to 10ms", "H+I 0 to 10ms"]
|
||||
--@ }
|
||||
-- EPP Data Write
|
||||
--@ {
|
||||
--@ "signal": [
|
||||
--@ { "name": "DEPP_Bus", "wave": "xx3....xxx", "data": ["Data"] },
|
||||
--@ { "name": "DEPP_WriteEnable", "wave": "1.0....1.." },
|
||||
--@ { "node": "...A...B", "phase": 0.15 },
|
||||
--@ { "name": "DEPP_DataEnable", "wave": "1..0...1.." },
|
||||
--@ { "node": "...E.F.H.I", "phase": 0.15 },
|
||||
--@ { "node": ".C.D.G", "phase": 0.15 },
|
||||
--@ { "name": "DEPP_Wait", "wave": "x0...1...0" }
|
||||
--@ ],
|
||||
--@ "head": {
|
||||
--@ "text": "EPP Data Write"
|
||||
--@ },
|
||||
--@ "foot": {
|
||||
--@ "text": "EPP Data Write Cycle Timing Diagram"
|
||||
--@ },
|
||||
--@ "edge": ["A+B min. 80 ns", "C+D min. 40ns", "E+F 0 to 10ms", "H+I 0 to 10ms"]
|
||||
--@ }
|
||||
-- EPP Data Read
|
||||
--@ {
|
||||
--@ "signal": [
|
||||
--@ { "name": "DEPP_Bus", "wave": "zz...3...x", "data": ["Data"] },
|
||||
--@ { "node": "...J.K.L.M", "phase": 0.15 },
|
||||
--@ { "name": "DEPP_WriteEnable", "wave": "x1........" },
|
||||
--@ { "node": "...A...B", "phase": 0.15 },
|
||||
--@ { "name": "DEPP_DataEnable", "wave": "1..0...1.." },
|
||||
--@ { "node": "...E..FH.I", "phase": 0.15 },
|
||||
--@ { "node": ".C.D.G", "phase": 0.15 },
|
||||
--@ { "name": "DEPP_Wait", "wave": "x0....1..0" }
|
||||
--@ ],
|
||||
--@ "head": {
|
||||
--@ "text": "EPP Data Read"
|
||||
--@ },
|
||||
--@ "foot": {
|
||||
--@ "text": "EPP Data Read Cycle Timing Diagram"
|
||||
--@ },
|
||||
--@ "edge": ["A+B min. 80 ns", "C+D min. 40 ns", "E+F 0 to 10 ms", "H+I 0 to 10 ms", "J+K max. 20 ns", "L+M min. 20 ns"
|
||||
--@ ]
|
||||
--@ }
|
||||
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.all;
|
||||
use IEEE.NUMERIC_STD.all;
|
||||
|
||||
entity DEPP is
|
||||
generic (
|
||||
--@ Number of 8-bit registers
|
||||
--@ `DOut` and `DIn` are 8 times this width
|
||||
RegisterQuant : integer := 1
|
||||
);
|
||||
port (
|
||||
--@ Clock signal
|
||||
--@ Rising edge triggered
|
||||
@@ -49,102 +90,267 @@ entity DEPP is
|
||||
--@ Reset signal
|
||||
--@ `1` = reset, `0` = normal operation
|
||||
RST : in std_logic;
|
||||
--@ @virtualbus EPP-Interface EPP Interface
|
||||
--@ @virtualbus EPP-Interface @dir out EPP Interface
|
||||
--@ Address strobe
|
||||
DEPP_AddressEnable : in std_logic;
|
||||
--@ Data strobe
|
||||
DEPP_DataEnable : in std_logic;
|
||||
--@ Transfer direction control
|
||||
--@ `1` = read (Host from DEPP), `0` = write (Host to DEPP)
|
||||
--@
|
||||
--@ `1` = read (Host from DEPP);
|
||||
--@ `0` = write (Host to DEPP)
|
||||
DEPP_WriteEnable : in std_logic;
|
||||
--@ Handshake signal
|
||||
--@ : `0` = ready for new cycle, `1` = closing current cycle; Keep the signal low to delay the cycle length
|
||||
DEPP_Wait : out std_logic;
|
||||
--@ Data/Adress bus
|
||||
--@
|
||||
--@ `0` = ready for new cycle;
|
||||
--@ `1` = closing current cycle and not ready for new cycle
|
||||
--@
|
||||
--@ Keep the signal low to delay the cycle length
|
||||
DEPP_Wait : out std_logic := '1';
|
||||
--@ Data/Adress bus;
|
||||
--@ Tri-state
|
||||
DEPP_Bus : inout std_logic_vector(7 downto 0) := (others => 'Z');
|
||||
--@ @end
|
||||
--@ Data output
|
||||
DOut : out std_logic_vector((RegisterQuant * 8) - 1 downto 0);
|
||||
--@ @virtualbus FIFO-Data-Out @dir out Data & Address Output. FIFO compatible interface
|
||||
--@ Data output corosponding to the address
|
||||
DataOutFifo_Data : out std_logic_vector(7 downto 0);
|
||||
--@ Address output
|
||||
DataOutFifo_Address : out std_logic_vector(7 downto 0);
|
||||
--@ Valid data & adress output if `1`. Is only 1 cycle valid
|
||||
DataOutFifo_WriteEnable : out std_logic;
|
||||
--@ If `1` the module delays the bus
|
||||
--@ and dont rise the `WriteEnable` signal
|
||||
DataOutFifo_FullFlag : in std_logic;
|
||||
--@ @end
|
||||
--@ @virtualbus FIFO-Data-In Data input. FIFO compatible interface
|
||||
--@ Data input
|
||||
DIn : in std_logic_vector((RegisterQuant * 8) - 1 downto 0));
|
||||
DataInFifo_Data : in std_logic_vector(7 downto 0);
|
||||
--@ If the fifo is not empty, the module will read the data
|
||||
DataInFifo_EmptyFlag : in std_logic;
|
||||
--@ Is one cycle `1` to indicate that the data is read
|
||||
DataInFifo_ReadEnable : out std_logic;
|
||||
--@ @end
|
||||
--@ @virtualbus FIFO-Address-Out @dir out Request address output. FIFO compatible interface
|
||||
--@ Address output for read requests
|
||||
AddressOutFifo_Data : out std_logic_vector(7 downto 0);
|
||||
--@ Valid address output if `1`. Is only 1 cycle valid
|
||||
AddressOutFifo_WriteEnable : out std_logic;
|
||||
--@ If `1` the module delays the bus
|
||||
--@ and dont rise the `RequestEnable` signal
|
||||
AddressOutFifo_FullFlag : in std_logic
|
||||
--@ @end
|
||||
);
|
||||
end DEPP;
|
||||
|
||||
architecture Behavioral of DEPP is
|
||||
|
||||
--@ Function to calculate the number of bits needed to address the `N` registers
|
||||
function min_bits_for_states(N : integer) return integer is
|
||||
begin
|
||||
if (N <= 2) then
|
||||
return 1;
|
||||
else
|
||||
if (N mod 2 = 0) then
|
||||
return 1 + min_bits_for_states(N/2);
|
||||
else
|
||||
return 1 + min_bits_for_states((N + 1)/2);
|
||||
end if;
|
||||
end if;
|
||||
end function min_bits_for_states;
|
||||
--@ Catch the address as long as the mode (read/write) has not yet been decided.
|
||||
signal TempAddressRegister : std_logic_vector(7 downto 0) := (others => '0');
|
||||
|
||||
type RegisterType is array(RegisterQuant - 1 downto 0)
|
||||
of std_logic_vector(7 downto 0);
|
||||
--@ Shift register for the rising/falling edge detection of the `DEPP_AddressEnable` signal
|
||||
signal EPP_AddressEnableShiftRegister : std_logic_vector(1 downto 0) := (others => '0');
|
||||
--@ Shift register for the rising/falling edge detection of the `DEPP_DataEnable` signal
|
||||
signal EPP_DataEnableShiftRegister : std_logic_vector(1 downto 0) := (others => '0');
|
||||
|
||||
signal RegistersIn : RegisterType;
|
||||
signal RegistersOut : RegisterType;
|
||||
--@ The states of the main state machine
|
||||
type ModeType is (Idle, RequestActive, SetData, WriteActive, WaitForFallingDataEnable, WaitingForFallingAddressEnable, AdressActive);
|
||||
--@ The current state of the main state machine
|
||||
signal Mode : ModeType := Idle;
|
||||
|
||||
signal EPPDInternal : std_logic_vector(7 downto 0);
|
||||
signal Adress : std_logic_vector(min_bits_for_states(RegisterQuant) - 1 downto 0);
|
||||
|
||||
signal Intern_CE : std_logic := '1';
|
||||
signal Intern_RST : std_logic := '0';
|
||||
--@ The output signals for the output data fifo
|
||||
signal InterWriteEnableOut : std_logic := '0';
|
||||
--@ The output signals for the output address fifo
|
||||
signal InterRequestEnable : std_logic := '0';
|
||||
--@ Intermediary signal to start the address write cycle
|
||||
signal InterAddressEnable : std_logic := '0';
|
||||
--@ Negated `DataInFifo_EmptyFlag` signal
|
||||
signal DataInFifo_DataAviable : std_logic;
|
||||
begin
|
||||
|
||||
DEPP_Wait <= '1' when DEPP_DataEnable = '0' or DEPP_AddressEnable = '0' else
|
||||
'0';
|
||||
DataInFifo_DataAviable <= not DataInFifo_EmptyFlag;
|
||||
DataOutFifo_WriteEnable <= InterWriteEnableOut;
|
||||
AddressOutFifo_WriteEnable <= InterRequestEnable;
|
||||
|
||||
DEPP_Bus <= EPPDInternal when (DEPP_WriteEnable = '1') else
|
||||
"ZZZZZZZZ";
|
||||
|
||||
DEPP_AddrIn : process (DEPP_AddressEnable)
|
||||
begin
|
||||
if rising_edge(DEPP_AddressEnable) then
|
||||
if DEPP_WriteEnable = '0' then
|
||||
Adress <= DEPP_Bus(min_bits_for_states(RegisterQuant) - 1 downto 0);
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
DEPP_DIn : process (DEPP_DataEnable)
|
||||
begin
|
||||
if rising_edge(DEPP_DataEnable) then
|
||||
if DEPP_WriteEnable = '0' then
|
||||
RegistersOut(to_integer(unsigned(Adress))) <= DEPP_Bus;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
EPPDInternal <= RegistersIn(to_integer(unsigned(Adress)));
|
||||
|
||||
DOutRegister : process (CLK)
|
||||
--@ Shifts the value from the `DEPP_AddressEnable` signal into the `EPP_AddressEnableShiftRegister`
|
||||
--@ for the rising/falling edge detection.
|
||||
EPP_AddressEnableCatch : process (CLK)
|
||||
begin
|
||||
if rising_edge(CLK) then
|
||||
if Intern_RST = '1' then
|
||||
DOut <= (others => '0');
|
||||
elsif Intern_CE = '1' then
|
||||
for i in 0 to RegisterQuant - 1 loop
|
||||
DOut(((i + 1) * 8) - 1 downto ((i) * 8)) <= RegistersOut(i);
|
||||
end loop;
|
||||
if RST = '1' then
|
||||
EPP_AddressEnableShiftRegister <= (others => '0');
|
||||
elsif CE = '1' then
|
||||
EPP_AddressEnableShiftRegister <= EPP_AddressEnableShiftRegister(0) & DEPP_AddressEnable;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
DInRegister : process (CLK)
|
||||
--@ Shifts the value from the `DEPP_DataEnable` signal into the `EPP_DataEnableShiftRegister`.
|
||||
--@ for the rising/falling edge detection.
|
||||
EPP_DataEnableCatch : process (CLK)
|
||||
begin
|
||||
if rising_edge(CLK) then
|
||||
if Intern_RST = '1' then
|
||||
null;
|
||||
elsif Intern_CE = '1' then
|
||||
for i in 0 to RegisterQuant - 1 loop
|
||||
RegistersIn(i) <= DIn(((i + 1) * 8) - 1 downto ((i) * 8));
|
||||
end loop;
|
||||
if RST = '1' then
|
||||
EPP_DataEnableShiftRegister <= (others => '0');
|
||||
elsif CE = '1' then
|
||||
EPP_DataEnableShiftRegister <= EPP_DataEnableShiftRegister(0) & DEPP_DataEnable;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
--@ Redirection of the `DataInFifo_EmptyFlag` signal to the `DataInFifo_ReadEnable` signal
|
||||
--@ if in the `RequestActive` mode: Minimize the latency of the data read.
|
||||
DataInFIFOMinimizeLatency : process (Mode, DataInFifo_DataAviable)
|
||||
begin
|
||||
if Mode = RequestActive then
|
||||
DataInFifo_ReadEnable <= DataInFifo_DataAviable;
|
||||
else
|
||||
DataInFifo_ReadEnable <= '0';
|
||||
end if;
|
||||
end process;
|
||||
|
||||
EPP_WaitManagement : process (CLK)
|
||||
begin
|
||||
if rising_edge(CLK) then
|
||||
if RST = '1' then
|
||||
DEPP_Wait <= '1';
|
||||
DEPP_Bus <= (others => 'Z');
|
||||
Mode <= Idle;
|
||||
elsif CE = '1' then
|
||||
case Mode is
|
||||
when Idle =>
|
||||
--@ In idle state the module waits for the beginning of a new cycle
|
||||
--@ like write address, write data or read data.
|
||||
--@ A new cycle is signaled via the signals `InterRequestEnable`,
|
||||
--@ `InterWriteEnableOut` and `InterAddressEnable` provided by the
|
||||
--@ `EPP_AddressCatch`, `EPP_ReciveData` and `EPP_ReciveRequest` processes.
|
||||
|
||||
DEPP_Bus <= (others => 'Z');
|
||||
--@ If the data or address output fifo is full the module signals the host to wait.
|
||||
DEPP_Wait <= DataOutFifo_FullFlag or AddressOutFifo_FullFlag;
|
||||
|
||||
if InterRequestEnable = '1' then
|
||||
--@ Start the read cycle
|
||||
Mode <= RequestActive;
|
||||
DEPP_Wait <= '0';
|
||||
elsif InterWriteEnableOut = '1' then
|
||||
--@ Start the write cycle
|
||||
Mode <= WaitForFallingDataEnable;
|
||||
elsif InterAddressEnable = '1' then
|
||||
--@ Start the address write cycle
|
||||
Mode <= WaitingForFallingAddressEnable;
|
||||
end if;
|
||||
when AdressActive =>
|
||||
--@ Intermediary state to hold the `DEPP_Wait` minimum one cycle high.
|
||||
Mode <= WaitingForFallingAddressEnable;
|
||||
when WriteActive =>
|
||||
--@ Intermediary state to hold the `DEPP_Wait` minimum one cycle high.
|
||||
Mode <= WaitForFallingDataEnable;
|
||||
when RequestActive =>
|
||||
DEPP_Wait <= '0';
|
||||
if DataInFifo_DataAviable = '1' then
|
||||
Mode <= SetData;
|
||||
end if;
|
||||
when SetData =>
|
||||
DEPP_Bus <= DataInFifo_Data;
|
||||
Mode <= WaitForFallingDataEnable;
|
||||
when WaitForFallingDataEnable =>
|
||||
DEPP_Wait <= '1';
|
||||
if EPP_DataEnableShiftRegister = "01" then
|
||||
Mode <= Idle;
|
||||
elsif (EPP_DataEnableShiftRegister = "11") and (EPP_AddressEnableShiftRegister = "11") then
|
||||
Mode <= Idle;
|
||||
end if;
|
||||
when WaitingForFallingAddressEnable =>
|
||||
DEPP_Wait <= '1';
|
||||
if EPP_AddressEnableShiftRegister = "01" then
|
||||
Mode <= Idle;
|
||||
elsif (EPP_DataEnableShiftRegister = "11") and (EPP_AddressEnableShiftRegister = "11") then
|
||||
Mode <= Idle;
|
||||
end if;
|
||||
when others =>
|
||||
DEPP_Wait <= '1';
|
||||
DEPP_Bus <= (others => 'Z');
|
||||
Mode <= Idle;
|
||||
end case;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
--@ Address write cycle:
|
||||
--@ If the `DEPP_AddressEnable` signal rises,
|
||||
--@ he `DEPP_WriteEnable` signal is low and the module is in idle state
|
||||
--@ the `DEPP_Bus` is stored in the `TempAddressRegister`.
|
||||
EPP_AddressCatch : process (CLK)
|
||||
begin
|
||||
if rising_edge(CLK) then
|
||||
if RST = '1' then
|
||||
TempAddressRegister <= (others => '0');
|
||||
InterAddressEnable <= '0';
|
||||
elsif CE = '1' then
|
||||
-- Self reset the `InterAddressEnableRst` signal after one cycle high.
|
||||
if InterAddressEnable = '1' then
|
||||
InterAddressEnable <= '0';
|
||||
end if;
|
||||
|
||||
if (EPP_AddressEnableShiftRegister = "10") and (DEPP_WriteEnable = '0') and (Mode = Idle) then
|
||||
TempAddressRegister <= DEPP_Bus;
|
||||
InterAddressEnable <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
--@ Data write cycle:
|
||||
--@ If the `DEPP_DataEnable` signal rises,
|
||||
--@ the `DEPP_WriteEnable` signal is low
|
||||
--@ and the module is in idle state
|
||||
--@ the `DEPP_Bus` is stored in the `DataOut`,
|
||||
--@ the `TempAddressRegister` is stored in the `AddressOut`
|
||||
--@ and the `WriteEnableOut` signal is set to `1`.
|
||||
EPP_ReciveData : process (CLK)
|
||||
begin
|
||||
if rising_edge(CLK) then
|
||||
if RST = '1' then
|
||||
DataOutFifo_Address <= (others => '0');
|
||||
DataOutFifo_Data <= (others => '0');
|
||||
InterWriteEnableOut <= '0';
|
||||
elsif CE = '1' then
|
||||
-- Self reset the `WriteEnableOut` signal after one cycle high.
|
||||
if InterWriteEnableOut = '1' then
|
||||
InterWriteEnableOut <= '0';
|
||||
end if;
|
||||
|
||||
if (EPP_DataEnableShiftRegister = "10") and (DEPP_WriteEnable = '0') and (Mode = Idle) then
|
||||
DataOutFifo_Address <= TempAddressRegister;
|
||||
DataOutFifo_Data <= DEPP_Bus;
|
||||
InterWriteEnableOut <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
--@ Data read cycle:
|
||||
--@ If the `DEPP_DataEnable` signal rises,
|
||||
--@ the `DEPP_WriteEnable` signal is high (read)
|
||||
--@ and the module is in idle state
|
||||
--@ the `TempAddressRegister` is stored in the `RequestAddress`
|
||||
--@ and the `RequestEnable` signal is set to `1`.
|
||||
EPP_ReciveRequest : process (CLK)
|
||||
begin
|
||||
if rising_edge(CLK) then
|
||||
if RST = '1' then
|
||||
AddressOutFifo_Data <= (others => '0');
|
||||
InterRequestEnable <= '0';
|
||||
elsif CE = '1' then
|
||||
-- Self reset the `RequestEnable` signal after one cycle high.
|
||||
if InterRequestEnable = '1' then
|
||||
InterRequestEnable <= '0';
|
||||
end if;
|
||||
|
||||
if (EPP_DataEnableShiftRegister = "10") and (DEPP_WriteEnable = '1') and (Mode = Idle) then
|
||||
AddressOutFifo_Data <= TempAddressRegister;
|
||||
InterRequestEnable <= '1';
|
||||
end if;
|
||||
end if;
|
||||
end if;
|
||||
end process;
|
||||
|
||||
59
code/Nexys2Test.ucf
Normal file
59
code/Nexys2Test.ucf
Normal file
@@ -0,0 +1,59 @@
|
||||
### Pin Constraints for the Nexys 2 Board ###
|
||||
NET CLK LOC = B8;
|
||||
NET CLK TNM_NET = CLOCK;
|
||||
TIMESPEC TS_CLOCK = PERIOD CLOCK 50 MHz HIGH 50 %;
|
||||
|
||||
NET "RST" LOC = "B18"; # BTN0
|
||||
NET "DataOutFullFlag" LOC = "D18"; # BTN1
|
||||
NET "RequestFullFlag" LOC = "E18"; # BTN2
|
||||
|
||||
NET "LED<0>" LOC = "J14";
|
||||
NET "LED<1>" LOC = "J15";
|
||||
NET "LED<2>" LOC = "K15";
|
||||
NET "LED<3>" LOC = "K14";
|
||||
NET "LED<4>" LOC = "E16";
|
||||
NET "LED<5>" LOC = "P16";
|
||||
NET "LED<6>" LOC = "E4";
|
||||
NET "LED<7>" LOC = "P4";
|
||||
|
||||
NET "Switches<0>" LOC = "G18";
|
||||
NET "Switches<1>" LOC = "H18";
|
||||
NET "Switches<2>" LOC = "K18";
|
||||
NET "Switches<3>" LOC = "K17";
|
||||
NET "Switches<4>" LOC = "L14";
|
||||
NET "Switches<5>" LOC = "L13";
|
||||
NET "Switches<6>" LOC = "N17";
|
||||
NET "Switches<7>" LOC = "R17";
|
||||
### ##################################### ###
|
||||
|
||||
### DEPP Interface ###
|
||||
NET "DEPP_AddressEnable" LOC = "V14";
|
||||
NET "DEPP_DataEnable" LOC = "U14";
|
||||
NET "DEPP_WriteEnable" LOC = "V16";
|
||||
NET "DEPP_Wait" LOC = "N9";
|
||||
|
||||
NET "DEPP_Bus<0>" LOC = "R14";
|
||||
NET "DEPP_Bus<1>" LOC = "R13";
|
||||
NET "DEPP_Bus<2>" LOC = "P13";
|
||||
NET "DEPP_Bus<3>" LOC = "T12";
|
||||
NET "DEPP_Bus<4>" LOC = "N11";
|
||||
NET "DEPP_Bus<5>" LOC = "R11";
|
||||
NET "DEPP_Bus<6>" LOC = "P10";
|
||||
NET "DEPP_Bus<7>" LOC = "R10";
|
||||
### ############## ###
|
||||
|
||||
### Logik Analyzer ###
|
||||
NET "LA_AddressEnable" LOC = "L15"; # JA 0
|
||||
NET "LA_DataEnable" LOC = "K12"; # JA 1
|
||||
NET "LA_WriteEnable" LOC = "L17"; # JA 2
|
||||
NET "LA_Wait" LOC = "M15"; # JA 3
|
||||
|
||||
NET "LA_Bus<0>" LOC = "M13"; # JB 0
|
||||
NET "LA_Bus<1>" LOC = "R18"; # JB 1
|
||||
NET "LA_Bus<2>" LOC = "R15"; # JB 2
|
||||
NET "LA_Bus<3>" LOC = "T17"; # JB 3
|
||||
NET "LA_Bus<4>" LOC = "P17"; # JB 4
|
||||
NET "LA_Bus<5>" LOC = "R16"; # JB 5
|
||||
NET "LA_Bus<6>" LOC = "T18"; # JB 6
|
||||
NET "LA_Bus<7>" LOC = "U18"; # JB 7
|
||||
### ############## ###
|
||||
101
code/Nexys2Test.vhd
Normal file
101
code/Nexys2Test.vhd
Normal file
@@ -0,0 +1,101 @@
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.all;
|
||||
use IEEE.NUMERIC_STD.all;
|
||||
|
||||
entity Nexys2Test is
|
||||
port (
|
||||
CLK : in std_logic;
|
||||
RST : in std_logic;
|
||||
LED : out std_logic_vector(7 downto 0);
|
||||
Switches : in std_logic_vector(7 downto 0);
|
||||
DataOutFullFlag : in std_logic;
|
||||
RequestFullFlag : in std_logic;
|
||||
-- Logic Analyzer
|
||||
LA_AddressEnable : out std_logic;
|
||||
LA_DataEnable : out std_logic;
|
||||
LA_WriteEnable : out std_logic;
|
||||
LA_Wait : out std_logic;
|
||||
LA_Bus : inout std_logic_vector(7 downto 0);
|
||||
-- EPP Interface
|
||||
DEPP_AddressEnable : in std_logic;
|
||||
DEPP_DataEnable : in std_logic;
|
||||
DEPP_WriteEnable : in std_logic;
|
||||
DEPP_Wait : out std_logic;
|
||||
DEPP_Bus : inout std_logic_vector(7 downto 0) := (others => 'Z')
|
||||
);
|
||||
end Nexys2Test;
|
||||
|
||||
architecture Behavioral of Nexys2Test is
|
||||
|
||||
component DEPP
|
||||
port (
|
||||
CLK : in std_logic;
|
||||
CE : in std_logic;
|
||||
RST : in std_logic;
|
||||
DEPP_AddressEnable : in std_logic;
|
||||
DEPP_DataEnable : in std_logic;
|
||||
DEPP_WriteEnable : in std_logic;
|
||||
DEPP_Wait : out std_logic;
|
||||
DEPP_Bus : inout std_logic_vector(7 downto 0);
|
||||
DataOutFifo_Data : out std_logic_vector(7 downto 0);
|
||||
DataOutFifo_Address : out std_logic_vector(7 downto 0);
|
||||
DataOutFifo_WriteEnable : out std_logic;
|
||||
DataOutFifo_FullFlag : in std_logic;
|
||||
DataInFifo_Data : in std_logic_vector(7 downto 0);
|
||||
DataInFifo_EmptyFlag : in std_logic;
|
||||
DataInFifo_ReadEnable : out std_logic;
|
||||
AddressOutFifo_Data : out std_logic_vector(7 downto 0);
|
||||
AddressOutFifo_WriteEnable : out std_logic;
|
||||
AddressOutFifo_FullFlag : in std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
signal InterLED : std_logic_vector(7 downto 0);
|
||||
signal InterSwitches : std_logic_vector(7 downto 0);
|
||||
signal DataAviable : std_logic;
|
||||
signal InternWait : std_logic;
|
||||
signal InternRST : std_logic;
|
||||
|
||||
signal EPP_Bus : std_logic_vector(7 downto 0);
|
||||
begin
|
||||
|
||||
DEPP_inst : DEPP
|
||||
port map(
|
||||
CLK => CLK,
|
||||
CE => '1',
|
||||
RST => InternRST,
|
||||
DEPP_AddressEnable => DEPP_AddressEnable,
|
||||
DEPP_DataEnable => DEPP_DataEnable,
|
||||
DEPP_WriteEnable => DEPP_WriteEnable,
|
||||
DEPP_Wait => InternWait,
|
||||
DEPP_Bus => EPP_Bus,
|
||||
DataOutFifo_Data => InterLED,
|
||||
DataOutFifo_Address => open,
|
||||
DataOutFifo_WriteEnable => DataAviable,
|
||||
DataOutFifo_FullFlag => DataOutFullFlag,
|
||||
DataInFifo_Data => InterSwitches,
|
||||
DataInFifo_EmptyFlag => '0',
|
||||
DataInFifo_ReadEnable => open,
|
||||
AddressOutFifo_Data => open,
|
||||
AddressOutFifo_WriteEnable => open,
|
||||
AddressOutFifo_FullFlag => RequestFullFlag
|
||||
);
|
||||
|
||||
DEPP_Wait <= InternWait;
|
||||
DEPP_Bus <= EPP_Bus;
|
||||
LA_Bus <= EPP_Bus;
|
||||
LA_AddressEnable <= DEPP_AddressEnable;
|
||||
LA_DataEnable <= DEPP_DataEnable;
|
||||
LA_WriteEnable <= DEPP_WriteEnable;
|
||||
LA_Wait <= InternWait;
|
||||
|
||||
process (CLK)
|
||||
begin
|
||||
if rising_edge(CLK) then
|
||||
LED <= InterLED;
|
||||
InternRST <= RST;
|
||||
|
||||
InterSwitches <= Switches;
|
||||
end if;
|
||||
end process;
|
||||
end Behavioral;
|
||||
@@ -1,73 +1,117 @@
|
||||
|
||||
# Entity: DEPP
|
||||
|
||||
- **File**: DEPP.vhd
|
||||
|
||||
## Diagram
|
||||
|
||||
|
||||
|
||||
|
||||
## Description
|
||||
|
||||
An EPP interface for Digilent FPGA boards
|
||||
This interface is designed to be used with the Digilent EPP interface
|
||||
and the Digilent Adept software.
|
||||
|
||||
**Measured data rate ≈ 4.68 kByte/s**
|
||||
|
||||
Below are diagrams of the EPP bus:
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
## Generics
|
||||
|
||||
| Generic name | Type | Value | Description |
|
||||
| ------------- | ------- | ----- | ------------------------------------------------------------------ |
|
||||
| RegisterQuant | integer | 1 | Number of 8-bit registers `DOut` and `DIn` are 8 times this width |
|
||||
|
||||
|
||||
## Ports
|
||||
|
||||
| Port name | Direction | Type | Description |
|
||||
| ------------- | --------- | -------------------------------------------------- | ------------------------------------------------- |
|
||||
| ---------------- | --------- | ----------- | ------------------------------------------------- |
|
||||
| CLK | in | std_logic | Clock signal Rising edge triggered |
|
||||
| CE | in | std_logic | Chip enable `1` = enabled, `0` = disabled |
|
||||
| RST | in | std_logic | Reset signal `1` = reset, `0` = normal operation |
|
||||
| DOut | out | std_logic_vector((RegisterQuant * 8) - 1 downto 0) | Data output |
|
||||
| DIn | in | std_logic_vector((RegisterQuant * 8) - 1 downto 0) | Data input |
|
||||
| EPP-Interface | in | Virtual bus | EPP Interface |
|
||||
| EPP-Interface | out | Virtual bus | EPP Interface |
|
||||
| FIFO-Data-Out | out | Virtual bus | Data & Address Output. FIFO compatible interface |
|
||||
| FIFO-Data-In | in | Virtual bus | Data input. FIFO compatible interface |
|
||||
| FIFO-Address-Out | out | Virtual bus | Request address output. FIFO compatible interface |
|
||||
|
||||
### Virtual Buses
|
||||
|
||||
#### EPP-Interface
|
||||
|
||||
| Port name | Direction | Type | Description |
|
||||
| ------------------ | --------- | ---------------------------- | ------------------------------------------------------------------------------------------------------------------------- |
|
||||
| ------------------ | --------- | ---------------------------- | ---------------------------------------------------------------------------------------------------------------------------------------------------------- |
|
||||
| DEPP_AddressEnable | in | std_logic | Address strobe |
|
||||
| DEPP_DataEnable | in | std_logic | Data strobe |
|
||||
| DEPP_WriteEnable | in | std_logic | Transfer direction control `1` = read (Host from DEPP), `0` = write (Host to DEPP) |
|
||||
| DEPP_Wait | out | std_logic | Handshake signal : `0` = ready for new cycle, `1` = closing current cycle; Keep the signal low to delay the cycle length |
|
||||
| DEPP_Bus | inout | std_logic_vector(7 downto 0) | Data/Adress bus |
|
||||
| DEPP_WriteEnable | in | std_logic | Transfer direction control<br> `1` = read (Host from DEPP); `0` = write (Host to DEPP) |
|
||||
| DEPP_Wait | out | std_logic | Handshake signal <br> `0` = ready for new cycle; `1` = closing current cycle and not ready for new cycle<br> Keep the signal low to delay the cycle length |
|
||||
| DEPP_Bus | inout | std_logic_vector(7 downto 0) | Data/Adress bus; Tri-state |
|
||||
|
||||
#### FIFO-Data-Out
|
||||
|
||||
| Port name | Direction | Type | Description |
|
||||
| ----------------------- | --------- | ---------------------------- | ----------------------------------------------------------------------- |
|
||||
| DataOutFifo_Data | out | std_logic_vector(7 downto 0) | Data output corosponding to the address |
|
||||
| DataOutFifo_Address | out | std_logic_vector(7 downto 0) | Address output |
|
||||
| DataOutFifo_WriteEnable | out | std_logic | Valid data & adress output if `1`. Is only 1 cycle valid |
|
||||
| DataOutFifo_FullFlag | in | std_logic | If `1` the module delays the bus and dont rise the `WriteEnable` signal |
|
||||
|
||||
#### FIFO-Data-In
|
||||
|
||||
| Port name | Direction | Type | Description |
|
||||
| --------------------- | --------- | ---------------------------- | ------------------------------------------------------- |
|
||||
| DataInFifo_Data | in | std_logic_vector(7 downto 0) | Data input |
|
||||
| DataInFifo_EmptyFlag | in | std_logic | If the fifo is not empty, the module will read the data |
|
||||
| DataInFifo_ReadEnable | out | std_logic | Is one cycle `1` to indicate that the data is read |
|
||||
|
||||
#### FIFO-Address-Out
|
||||
|
||||
| Port name | Direction | Type | Description |
|
||||
| -------------------------- | --------- | ---------------------------- | ------------------------------------------------------------------------- |
|
||||
| AddressOutFifo_Data | out | std_logic_vector(7 downto 0) | Address output for read requests |
|
||||
| AddressOutFifo_WriteEnable | out | std_logic | Valid address output if `1`. Is only 1 cycle valid |
|
||||
| AddressOutFifo_FullFlag | in | std_logic | If `1` the module delays the bus and dont rise the `RequestEnable` signal |
|
||||
|
||||
## Signals
|
||||
|
||||
| Name | Type | Description |
|
||||
| ------------ | ----------------------------------------------------------------- | ----------- |
|
||||
| RegistersIn | RegisterType | |
|
||||
| RegistersOut | RegisterType | |
|
||||
| EPPDInternal | std_logic_vector(7 downto 0) | |
|
||||
| Adress | std_logic_vector(min_bits_for_states(RegisterQuant) - 1 downto 0) | |
|
||||
| Intern_CE | std_logic | |
|
||||
| Intern_RST | std_logic | |
|
||||
| ------------------------------ | ---------------------------- | --------------------------------------------------------------------------------------- |
|
||||
| TempAddressRegister | std_logic_vector(7 downto 0) | Catch the address as long as the mode (read/write) has not yet been decided. |
|
||||
| EPP_AddressEnableShiftRegister | std_logic_vector(1 downto 0) | Shift register for the rising/falling edge detection of the `DEPP_AddressEnable` signal |
|
||||
| EPP_DataEnableShiftRegister | std_logic_vector(1 downto 0) | Shift register for the rising/falling edge detection of the `DEPP_DataEnable` signal |
|
||||
| Mode | ModeType | The current state of the main state machine |
|
||||
| InterWriteEnableOut | std_logic | The output signals for the output data fifo |
|
||||
| InterRequestEnable | std_logic | The output signals for the output address fifo |
|
||||
| InterAddressEnable | std_logic | Intermediary signal to start the address write cycle |
|
||||
| DataInFifo_DataAviable | std_logic | Negated `DataInFifo_EmptyFlag` signal |
|
||||
|
||||
## Types
|
||||
|
||||
| Name | Type | Description |
|
||||
| ------------ | ---- | ----------- |
|
||||
| RegisterType | | |
|
||||
| -------- | ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- | ------------------------------------ |
|
||||
| ModeType | (Idle,<br><span style="padding-left:20px"> RequestActive,<br><span style="padding-left:20px"> SetData,<br><span style="padding-left:20px"> WriteActive,<br><span style="padding-left:20px"> WaitForFallingDataEnable,<br><span style="padding-left:20px"> WaitingForFallingAddressEnable,<br><span style="padding-left:20px"> AdressActive) | The states of the main state machine |
|
||||
|
||||
## Functions
|
||||
- min_bits_for_states <font id="function_arguments">(N : integer)</font> <font id="function_return">return integer</font>
|
||||
- Function to calculate the number of bits needed to address the `N` registers
|
||||
## Processes
|
||||
- DEPP_AddrIn: ( DEPP_AddressEnable )
|
||||
- DEPP_DIn: ( DEPP_DataEnable )
|
||||
- DOutRegister: ( CLK )
|
||||
- DInRegister: ( CLK )
|
||||
|
||||
- EPP_AddressEnableCatch: ( CLK )
|
||||
- **Description**
|
||||
Shifts the value from the `DEPP_AddressEnable` signal into the `EPP_AddressEnableShiftRegister` for the rising/falling edge detection.
|
||||
- EPP_DataEnableCatch: ( CLK )
|
||||
- **Description**
|
||||
Shifts the value from the `DEPP_DataEnable` signal into the `EPP_DataEnableShiftRegister`. for the rising/falling edge detection.
|
||||
- DataInFIFOMinimizeLatency: ( Mode, DataInFifo_DataAviable )
|
||||
- **Description**
|
||||
Redirection of the `DataInFifo_EmptyFlag` signal to the `DataInFifo_ReadEnable` signal if in the `RequestActive` mode: Minimize the latency of the data read.
|
||||
- EPP_WaitManagement: ( CLK )
|
||||
- EPP_AddressCatch: ( CLK )
|
||||
- **Description**
|
||||
Address write cycle: If the `DEPP_AddressEnable` signal rises, he `DEPP_WriteEnable` signal is low and the module is in idle state the `DEPP_Bus` is stored in the `TempAddressRegister`.
|
||||
- EPP_ReciveData: ( CLK )
|
||||
- **Description**
|
||||
Data write cycle: If the `DEPP_DataEnable` signal rises, the `DEPP_WriteEnable` signal is low and the module is in idle state the `DEPP_Bus` is stored in the `DataOut`, the `TempAddressRegister` is stored in the `AddressOut` and the `WriteEnableOut` signal is set to `1`.
|
||||
- EPP_ReciveRequest: ( CLK )
|
||||
- **Description**
|
||||
Data read cycle: If the `DEPP_DataEnable` signal rises, the `DEPP_WriteEnable` signal is high (read) and the module is in idle state the `TempAddressRegister` is stored in the `RequestAddress` and the `RequestEnable` signal is set to `1`.
|
||||
|
||||
## State machines
|
||||
|
||||
|
||||
|
||||
File diff suppressed because one or more lines are too long
|
Before Width: | Height: | Size: 5.9 KiB After Width: | Height: | Size: 5.6 KiB |
20
docs/DEPP/Waveforms/EPP Data Read.json
Normal file
20
docs/DEPP/Waveforms/EPP Data Read.json
Normal file
@@ -0,0 +1,20 @@
|
||||
{
|
||||
"signal": [
|
||||
{ "name": "DEPP_Bus", "wave": "zz...3...x", "data": ["Adress"] },
|
||||
{ "node": "...J.K.L.M", "phase": 0.15 },
|
||||
{ "name": "DEPP_WriteEnable", "wave": "x1........" },
|
||||
{ "node": "...A...B", "phase": 0.15 },
|
||||
{ "name": "DEPP_DataEnable", "wave": "1..0...1.." },
|
||||
{ "node": "...E..FH.I", "phase": 0.15 },
|
||||
{ "node": ".C.D.G", "phase": 0.15 },
|
||||
{ "name": "DEPP_Wait", "wave": "x0....1..0" }
|
||||
],
|
||||
"head": {
|
||||
"text": "EPP Data Read"
|
||||
},
|
||||
"foot": {
|
||||
"text": "EPP Data Read Cycle Timing Diagram"
|
||||
},
|
||||
"edge": ["A+B min. 80 ns", "C+D min. 40 ns", "E+F 0 to 10 ms", "H+I 0 to 10 ms", "J+K max. 20 ns", "L+M min. 20 ns"
|
||||
]
|
||||
}
|
||||
18
docs/DEPP/Waveforms/EPP Data Write.json
Normal file
18
docs/DEPP/Waveforms/EPP Data Write.json
Normal file
@@ -0,0 +1,18 @@
|
||||
{
|
||||
"signal": [
|
||||
{ "name": "DEPP_Bus", "wave": "xx3....xxx", "data": ["Adress"] },
|
||||
{ "name": "DEPP_WriteEnable", "wave": "1.0....1.." },
|
||||
{ "node": "...A...B", "phase": 0.15 },
|
||||
{ "name": "DEPP_DataEnable", "wave": "1..0...1.." },
|
||||
{ "node": "...E.F.H.I", "phase": 0.15 },
|
||||
{ "node": ".C.D.G", "phase": 0.15 },
|
||||
{ "name": "DEPP_Wait", "wave": "x0...1...0" }
|
||||
],
|
||||
"head": {
|
||||
"text": "EPP Data Write"
|
||||
},
|
||||
"foot": {
|
||||
"text": "EPP Data Write Cycle Timing Diagram"
|
||||
},
|
||||
"edge": ["A+B min. 80 ns", "C+D min. 40ns", "E+F 0 to 10ms", "H+I 0 to 10ms"]
|
||||
}
|
||||
145
docs/DEPP/fsm_DEPP_00.svg
Normal file
145
docs/DEPP/fsm_DEPP_00.svg
Normal file
@@ -0,0 +1,145 @@
|
||||
<?xml version="1.0" encoding="UTF-8" standalone="no"?>
|
||||
<!DOCTYPE svg PUBLIC "-//W3C//DTD SVG 1.1//EN"
|
||||
"http://www.w3.org/Graphics/SVG/1.1/DTD/svg11.dtd">
|
||||
<!-- Generated by graphviz version 2.40.1 (20161225.0304)
|
||||
-->
|
||||
<!-- Title: state transitions Pages: 1 -->
|
||||
<svg width="1127pt" height="352pt"
|
||||
viewBox="0.00 0.00 1127.00 352.00" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink">
|
||||
<g id="graph0" class="graph" transform="scale(1 1) rotate(0) translate(4 348)">
|
||||
<title>state transitions</title>
|
||||
<polygon fill="#ffffff" stroke="transparent" points="-4,4 -4,-348 1123,-348 1123,4 -4,4"/>
|
||||
<g id="clust1" class="cluster state regular">
|
||||
<title>cluster_Mode</title>
|
||||
<path fill="none" stroke="#000000" stroke-width="2" d="M20,-8C20,-8 1099,-8 1099,-8 1105,-8 1111,-14 1111,-20 1111,-20 1111,-324 1111,-324 1111,-330 1105,-336 1099,-336 1099,-336 20,-336 20,-336 14,-336 8,-330 8,-324 8,-324 8,-20 8,-20 8,-14 14,-8 20,-8"/>
|
||||
<text text-anchor="start" x="544.4964" y="-317.2" font-family="Helvetica,sans-Serif" font-size="12.00" fill="#000000">Mode</text>
|
||||
</g>
|
||||
<!-- Mode -->
|
||||
<!-- Idle -->
|
||||
<g id="node2" class="node state regular">
|
||||
<title>Idle</title>
|
||||
<polygon fill="#ffffff" fill-opacity="0.003922" stroke="transparent" stroke-width="2" points="920,-298 864,-298 864,-262 920,-262 920,-298"/>
|
||||
<text text-anchor="start" x="882.3304" y="-276.2" font-family="Helvetica,sans-Serif" font-size="12.00" fill="#000000">Idle</text>
|
||||
<path fill="none" stroke="#000000" stroke-width="2" d="M876.3333,-263C876.3333,-263 907.6667,-263 907.6667,-263 913.3333,-263 919,-268.6667 919,-274.3333 919,-274.3333 919,-285.6667 919,-285.6667 919,-291.3333 913.3333,-297 907.6667,-297 907.6667,-297 876.3333,-297 876.3333,-297 870.6667,-297 865,-291.3333 865,-285.6667 865,-285.6667 865,-274.3333 865,-274.3333 865,-268.6667 870.6667,-263 876.3333,-263"/>
|
||||
</g>
|
||||
<!-- RequestActive -->
|
||||
<g id="node5" class="node state regular">
|
||||
<title>RequestActive</title>
|
||||
<polygon fill="#ffffff" fill-opacity="0.003922" stroke="transparent" stroke-width="2" points="847.5,-216 748.5,-216 748.5,-180 847.5,-180 847.5,-216"/>
|
||||
<text text-anchor="start" x="759.824" y="-194.2" font-family="Helvetica,sans-Serif" font-size="12.00" fill="#000000">RequestActive</text>
|
||||
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</g>
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<!-- Idle->RequestActive -->
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<g id="edge1" class="edge transition">
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<title>Idle->RequestActive</title>
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<path fill="none" stroke="#000000" d="M899.9839,-261.5765C902.7166,-252.2428 903.807,-241.1849 898,-233 892.5846,-225.367 875.6733,-218.272 857.2613,-212.4933"/>
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<text text-anchor="start" x="902" y="-236" font-family="Helvetica,sans-Serif" font-size="10.00" fill="#000000">InterRequestEnable = '1'   </text>
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</g>
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<!-- WaitForFallingDataEnable -->
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<g id="node7" class="node state regular">
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<title>WaitForFallingDataEnable</title>
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<text text-anchor="start" x="516.9944" y="-30.2" font-family="Helvetica,sans-Serif" font-size="12.00" fill="#000000">WaitForFallingDataEnable</text>
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</g>
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<g id="edge2" class="edge transition">
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<title>Idle->WaitForFallingDataEnable</title>
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<text text-anchor="start" x="782" y="-154" font-family="Helvetica,sans-Serif" font-size="10.00" fill="#000000">InterWriteEnableOut = '1'   </text>
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</g>
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<!-- WaitingForFallingAddressEnable -->
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<g id="node8" class="node state regular">
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<title>WaitingForFallingAddressEnable</title>
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<text text-anchor="start" x="93.6568" y="-194.2" font-family="Helvetica,sans-Serif" font-size="12.00" fill="#000000">WaitingForFallingAddressEnable</text>
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<path fill="none" stroke="#000000" stroke-width="2" d="M95.3333,-181C95.3333,-181 266.6667,-181 266.6667,-181 272.3333,-181 278,-186.6667 278,-192.3333 278,-192.3333 278,-203.6667 278,-203.6667 278,-209.3333 272.3333,-215 266.6667,-215 266.6667,-215 95.3333,-215 95.3333,-215 89.6667,-215 84,-209.3333 84,-203.6667 84,-203.6667 84,-192.3333 84,-192.3333 84,-186.6667 89.6667,-181 95.3333,-181"/>
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</g>
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<!-- Idle->WaitingForFallingAddressEnable -->
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<g id="edge3" class="edge transition">
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<title>Idle->WaitingForFallingAddressEnable</title>
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<path fill="none" stroke="#000000" d="M863.566,-279.8389C725.3287,-278.9185 129.0183,-273.3132 102.485,-245 93.9132,-235.8531 98.0847,-227.8797 107.9583,-221.2253"/>
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<polygon fill="#000000" stroke="#000000" points="109.9548,-224.1186 116.9647,-216.1742 106.5307,-218.0132 109.9548,-224.1186"/>
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<text text-anchor="start" x="102" y="-236" font-family="Helvetica,sans-Serif" font-size="10.00" fill="#000000">InterAddressEnable = '1'   </text>
|
||||
</g>
|
||||
<!-- AdressActive -->
|
||||
<g id="node3" class="node state regular">
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||||
<title>AdressActive</title>
|
||||
<polygon fill="#ffffff" fill-opacity="0.003922" stroke="transparent" stroke-width="2" points="108,-298 16,-298 16,-262 108,-262 108,-298"/>
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<text text-anchor="start" x="26.9948" y="-276.2" font-family="Helvetica,sans-Serif" font-size="12.00" fill="#000000">AdressActive</text>
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<path fill="none" stroke="#000000" stroke-width="2" d="M28.3333,-263C28.3333,-263 95.6667,-263 95.6667,-263 101.3333,-263 107,-268.6667 107,-274.3333 107,-274.3333 107,-285.6667 107,-285.6667 107,-291.3333 101.3333,-297 95.6667,-297 95.6667,-297 28.3333,-297 28.3333,-297 22.6667,-297 17,-291.3333 17,-285.6667 17,-285.6667 17,-274.3333 17,-274.3333 17,-268.6667 22.6667,-263 28.3333,-263"/>
|
||||
</g>
|
||||
<!-- AdressActive->WaitingForFallingAddressEnable -->
|
||||
<g id="edge4" class="edge transition">
|
||||
<title>AdressActive->WaitingForFallingAddressEnable</title>
|
||||
<path fill="none" stroke="#000000" d="M53.6738,-261.651C50.7763,-252.3377 49.5047,-241.2756 55.221,-233 58.7223,-227.9311 66.4079,-223.4367 76.343,-219.5015"/>
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<polygon fill="#000000" stroke="#000000" points="77.7991,-222.6982 86.0438,-216.0442 75.4492,-216.1044 77.7991,-222.6982"/>
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<text text-anchor="middle" x="56.3895" y="-236" font-family="Helvetica,sans-Serif" font-size="10.00" fill="#000000"> </text>
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</g>
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<!-- WriteActive -->
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<g id="node4" class="node state regular">
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||||
<title>WriteActive</title>
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<polygon fill="#ffffff" fill-opacity="0.003922" stroke="transparent" stroke-width="2" points="131,-134 49,-134 49,-98 131,-98 131,-134"/>
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<text text-anchor="start" x="59.6694" y="-112.2" font-family="Helvetica,sans-Serif" font-size="12.00" fill="#000000">WriteActive</text>
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<path fill="none" stroke="#000000" stroke-width="2" d="M61.3333,-99C61.3333,-99 118.6667,-99 118.6667,-99 124.3333,-99 130,-104.6667 130,-110.3333 130,-110.3333 130,-121.6667 130,-121.6667 130,-127.3333 124.3333,-133 118.6667,-133 118.6667,-133 61.3333,-133 61.3333,-133 55.6667,-133 50,-127.3333 50,-121.6667 50,-121.6667 50,-110.3333 50,-110.3333 50,-104.6667 55.6667,-99 61.3333,-99"/>
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</g>
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||||
<!-- WriteActive->WaitForFallingDataEnable -->
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||||
<g id="edge5" class="edge transition">
|
||||
<title>WriteActive->WaitForFallingDataEnable</title>
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||||
<path fill="none" stroke="#000000" d="M102.9925,-97.8732C113.4987,-84.8054 129.5431,-68.099 148,-60 178.8675,-46.4551 376.0667,-39.2249 495.4183,-36.0429"/>
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<polygon fill="#000000" stroke="#000000" points="495.7448,-39.5356 505.6497,-35.7749 495.5614,-32.538 495.7448,-39.5356"/>
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<text text-anchor="middle" x="133.3895" y="-72" font-family="Helvetica,sans-Serif" font-size="10.00" fill="#000000"> </text>
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</g>
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||||
<!-- SetData -->
|
||||
<g id="node6" class="node state regular">
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<title>SetData</title>
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<polygon fill="#ffffff" fill-opacity="0.003922" stroke="transparent" stroke-width="2" points="619.5,-134 554.5,-134 554.5,-98 619.5,-98 619.5,-134"/>
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<text text-anchor="start" x="565.8262" y="-112.2" font-family="Helvetica,sans-Serif" font-size="12.00" fill="#000000">SetData</text>
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<path fill="none" stroke="#000000" stroke-width="2" d="M566.8333,-99C566.8333,-99 607.1667,-99 607.1667,-99 612.8333,-99 618.5,-104.6667 618.5,-110.3333 618.5,-110.3333 618.5,-121.6667 618.5,-121.6667 618.5,-127.3333 612.8333,-133 607.1667,-133 607.1667,-133 566.8333,-133 566.8333,-133 561.1667,-133 555.5,-127.3333 555.5,-121.6667 555.5,-121.6667 555.5,-110.3333 555.5,-110.3333 555.5,-104.6667 561.1667,-99 566.8333,-99"/>
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||||
</g>
|
||||
<!-- RequestActive->SetData -->
|
||||
<g id="edge6" class="edge transition">
|
||||
<title>RequestActive->SetData</title>
|
||||
<path fill="none" stroke="#000000" d="M748.1387,-194.6548C697.9512,-190.3215 625.0074,-181.0743 603.71,-163 597.8995,-158.0689 594.1092,-150.9742 591.6368,-143.7861"/>
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<polygon fill="#000000" stroke="#000000" points="595.0112,-142.8563 589.0163,-134.1206 588.2551,-144.688 595.0112,-142.8563"/>
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<text text-anchor="start" x="603" y="-154" font-family="Helvetica,sans-Serif" font-size="10.00" fill="#000000">DataInFifo_DataAviable = '1'   </text>
|
||||
</g>
|
||||
<!-- SetData->WaitForFallingDataEnable -->
|
||||
<g id="edge7" class="edge transition">
|
||||
<title>SetData->WaitForFallingDataEnable</title>
|
||||
<path fill="none" stroke="#000000" d="M587,-97.8015C587,-87.3976 587,-74.1215 587,-62.3768"/>
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<polygon fill="#000000" stroke="#000000" points="590.5001,-62.1476 587,-52.1476 583.5001,-62.1476 590.5001,-62.1476"/>
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<text text-anchor="middle" x="588.3895" y="-72" font-family="Helvetica,sans-Serif" font-size="10.00" fill="#000000"> </text>
|
||||
</g>
|
||||
<!-- WaitForFallingDataEnable->Idle -->
|
||||
<g id="edge8" class="edge transition">
|
||||
<title>WaitForFallingDataEnable->Idle</title>
|
||||
<path fill="none" stroke="#000000" d="M668.2862,-35.8361C769.716,-39.237 930,-48.762 930,-75 930,-142.5 930,-142.5 930,-142.5 930,-203.1048 1007.1476,-177.7252 1032,-233 1034.1871,-237.8643 1034.4752,-240.2758 1032,-245 1022.5408,-263.0535 968.5544,-272.2966 930.4611,-276.6359"/>
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<text text-anchor="start" x="933" y="-154" font-family="Helvetica,sans-Serif" font-size="10.00" fill="#000000">EPP_DataEnableShiftRegister = "01"   </text>
|
||||
</g>
|
||||
<!-- WaitForFallingDataEnable->Idle -->
|
||||
<g id="edge9" class="edge transition">
|
||||
<title>WaitForFallingDataEnable->Idle</title>
|
||||
<path fill="none" stroke="#000000" d="M505.8101,-37.6698C380.4322,-43.8843 154,-57.5265 154,-75 154,-142.5 154,-142.5 154,-142.5 154,-164.9879 178.5232,-157.2326 200.259,-163 204.8924,-164.2294 883.6029,-229.6178 887,-233 891.8084,-237.7872 894.0322,-244.3853 894.8394,-251.1251"/>
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<polygon fill="#000000" stroke="#000000" points="891.3527,-251.6864 895.1098,-261.5927 898.3503,-251.5056 891.3527,-251.6864"/>
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<text text-anchor="start" x="200" y="-154" font-family="Helvetica,sans-Serif" font-size="10.00" fill="#000000">(EPP_DataEnableShiftRegister = "11") and (EPP_AddressEnableShiftRegister = "11")   </text>
|
||||
</g>
|
||||
<!-- WaitingForFallingAddressEnable->Idle -->
|
||||
<g id="edge10" class="edge transition">
|
||||
<title>WaitingForFallingAddressEnable->Idle</title>
|
||||
<path fill="none" stroke="#000000" d="M205.9437,-216.0653C221.858,-226.5398 243.3882,-238.8433 264.457,-245 320.8058,-261.4663 725.8724,-274.9814 853.5555,-278.8711"/>
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<text text-anchor="start" x="264" y="-236" font-family="Helvetica,sans-Serif" font-size="10.00" fill="#000000">EPP_AddressEnableShiftRegister = "01"   </text>
|
||||
</g>
|
||||
<!-- WaitingForFallingAddressEnable->Idle -->
|
||||
<g id="edge11" class="edge transition">
|
||||
<title>WaitingForFallingAddressEnable->Idle</title>
|
||||
<path fill="none" stroke="#000000" d="M279.161,-207.1491C331.3792,-212.879 396.5036,-221.4016 454,-233 473.5583,-236.9454 477.6274,-241.4375 497.259,-245 626.3595,-268.4277 782.1784,-276.3738 853.261,-278.9031"/>
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<text text-anchor="start" x="497" y="-236" font-family="Helvetica,sans-Serif" font-size="10.00" fill="#000000">(EPP_DataEnableShiftRegister = "11") and (EPP_AddressEnableShiftRegister = "11")   </text>
|
||||
</g>
|
||||
</g>
|
||||
</svg>
|
||||
|
After Width: | Height: | Size: 13 KiB |
1
docs/DEPP/wavedrom_91sO2.svg
Normal file
1
docs/DEPP/wavedrom_91sO2.svg
Normal file
File diff suppressed because one or more lines are too long
|
After Width: | Height: | Size: 48 KiB |
|
Before Width: | Height: | Size: 47 KiB After Width: | Height: | Size: 47 KiB |
1
docs/DEPP/wavedrom_ypdi1.svg
Normal file
1
docs/DEPP/wavedrom_ypdi1.svg
Normal file
File diff suppressed because one or more lines are too long
|
After Width: | Height: | Size: 47 KiB |
BIN
docs/Logic Analyzer Captures/Address Write Cycle.webp
Normal file
BIN
docs/Logic Analyzer Captures/Address Write Cycle.webp
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 224 KiB |
BIN
docs/Logic Analyzer Captures/Data Read Cycle.webp
Normal file
BIN
docs/Logic Analyzer Captures/Data Read Cycle.webp
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 201 KiB |
BIN
docs/Logic Analyzer Captures/Data Write Cycle.webp
Normal file
BIN
docs/Logic Analyzer Captures/Data Write Cycle.webp
Normal file
Binary file not shown.
|
After Width: | Height: | Size: 202 KiB |
@@ -12,10 +12,10 @@ TARGET_PART = xc3s1200e-4-fg320
|
||||
XILINX = /opt/Xilinx/14.7/ISE_DS/ISE
|
||||
|
||||
# Optional the name of the top module (default is the project name)
|
||||
# TOPLEVEL =
|
||||
TOPLEVEL = Nexys2Test
|
||||
|
||||
# Optional the name of the ucf file (default is the project name)
|
||||
CONSTRAINTS = code/DEPP.ucf
|
||||
CONSTRAINTS = code/Nexys2Test.ucf
|
||||
|
||||
## ## ## ## ## ## ## ##
|
||||
# ---------------------
|
||||
@@ -25,6 +25,7 @@ CONSTRAINTS = code/DEPP.ucf
|
||||
# @example `VSOURCE += src/main.v` (add a single Verilog file per line)
|
||||
# @example `VHDSOURCE += src/main.vhd` (add a single VHDL file per line)
|
||||
|
||||
VHDSOURCE += code/Nexys2Test.vhd
|
||||
VHDSOURCE += code/DEPP.vhd
|
||||
|
||||
## ## ## ## ## ## ## ##
|
||||
@@ -81,5 +82,8 @@ DJTG_INDEX = 0
|
||||
# The index of the flash device for the `flash` target
|
||||
DJTG_FLASH_INDEX = 1
|
||||
|
||||
# Pre-programmer command
|
||||
PROGRAMMER_PRE = yes Y | sudo
|
||||
|
||||
## ## ## ## ## ## ## ##
|
||||
# ---------------------
|
||||
Reference in New Issue
Block a user